UNIVERSITY of PENNSYLVANIA
DEPARTMENT OF ELECTRICAL and SYSTEMS ENGINEERING

ESE 201: Principles of Digital Design Laboratory

Jan Van der Spiegel

Fall  2005


Do not print copies of this material on the CETS or ESE  printers.


General
Policies

 


Blackboard

Syllabus (Labs)

Lab Safety
Lab Procedures

Guidelines
Lab Reports
Lab Notebook


Tutorials

Foundation
VHDL primer
ABEL primer


Prototyping board

Digilab board 
XS40 board 
XS95 board 
FPGA demoboard


Device pins

XS10XL-84 pin 
(Spartan) 
XC4000-84 pin 
XC9500-84 pin


Links:
ESE200
Resources
Xilinx Answers
Xilinx Support
Xilinx: TechTips
Xilinx: F2.1i manual
Common mistakes



Description

The laboratory consists of hands-on assignments which accompany the lectures of ESE200. The goal is to illustrate concepts discussed in the class and to give the students the opportunity to build and test real systems.

The lab exercises will make use of the Xilinx Foundation(TM) System which is a a powerful state-of-the-art CAD tool for designing and implementating digital systems on Field Programmable devices (FGPAs or CPLDs). The ESE Undergraduate lab (Frederick Ketterer Lab) is equipped with both the Xilinx Foundation software tools and the Digilab boards to download and test the designs. The system consists of an integrated set of tools that allows one to capture designs (with schematic entry or a Hardware Description Language), simulate, implement and test them. The use of programmable logic devices takes away the tedious task of wire wrapping individual gates and allows one to concentrate on the creative part of designing the circuits.

The assignments will introduce you gradually to the Xilinx tools and will serve to illustrate the material covered in class. The first labs deal with combinational circuits and the last ones covers sequential circuits. When you read the lab assignments you will notice that there are several options for the implementation, depending which hardware board you will be using. Unless otherwise specified, you will be using the Digilab board.

Labs are done in groups of two, except for the on-line pre-lab that has to be done by each student (see also Lab Procedures).
 

The Educational Objectives of the Laboratory are:


1. To illustrate concepts of digital system design as discussed in the class (ESE200) through hands-on projects.
2. To develop skills, techniques and the use of state-of-the-art engineering tools (such as VHDL, Xilinx tools) to design and implement modern-day digital systems on FPGAs.
3. To learn to analyze the results of logic and timing simulations and learn to use these results to debug digital systems.
4. To learn to work in groups and communicate their results effectively through weekly written reports
.

Place

Frederick Ketterer Lab, room 204 Moore
Schedule
Tuesdays 3-6pm
Friday 3-6pm
Friday 12-3pm

Instructor

Prof. J. Van der Spiegel: (room 203 Moore)
Thursday: 4:00-5:30pm

Teaching Assistant: Mr. Zheng Yang (209 Moore); zhengy@seas

Teaching Assistant

        Zheng Yang
        Email: zhengy@seas.upenn.edu

Lab Assistants

Nathan Lazarus
Sam Starr
Rai M. Saloni

Luzy Zhang

Policies

The on-line pre-lab questions need to be answered prior to coming to the lab. The deadline is indicated in the lab-write up.  NO CREDIT will be given for submissions past the deadline! For grading policies consult the individual pre-labs. For late lab policies, please consult the Website in Blackboard.

The final grade will be based on your pre-lab performance, in-lab performance, Lab reports (see Lab Reports), Lab Notebooks and a final in-lab exam. If you have questions about the grading of the lab report, you have to contact  the instructor within one week after the  lab reports have been returned. After this week, no changes of grade will be made.

Using or attempting to use unauthorized assistance, material, or  lab results or solutions  (in part or whole)  is a violation of the Code of Academic Integrity and will result in a zero grade for the course.
 

Lab Syllabus (tentative)

    Fall 2005    
    Date Topic Pre-lab due on Tuesdays of 1st lab session
    Tue. Sept. 13& Fr. Sept. 16 Lab 1: Overview of the Xilinx Foundation tools:
    • Safety issues
    • Tutorials on Schematic entry and simulation of a Half Adder
    Tue. Sept. 13
    Sept. 20& 23 Lab 2: Full Adder Lab
    • Design and simulation of a Full Adder
    • Implementation of the Full Adder onto a FPGA
    • Testing
    Tue. Sept. 20
    Sept. 27& 28 Lab 3: Four bit Adder
    • Hierarchical design and macros
    • Design and simulation of a 4-bit adder
    Tue. Sept. 27
    Oct. 4 & 7 Lab 4: Implementation of the 4-bit adder
    • VHDL HDL (Hardware description language)
    • 7-segment decoder
    • Implementation using the FPGA Demoboard
    Tue. Oct. 4
    Oct. 11& 14 Lab 5: Carry Look-ahead Adder
    • Delays in ripple carry and carry look-ahead adders
    • Desing of a 16-bit carry look-ahead adder
    • Measuring delays in adders
    Tue. Oct. 11
    Oct. 25 (Tue section) & 28 Lab 6: Mini Project: ALU Design and Implementation
    • Design a 4-bit ALU using a bit-slice approach
    • Implement and test  the ALU
    Oct. 25 (2 weeks)
    Nov. 8 & 11 Lab 7: Counter design
    • Use of flip-flops for sequential circuit design
    • Design, implement and test a 4-bit up/down Johnson counter
    Tue. Nov. 8
    Nov. 15& 18 Lab 8: Design and Implementation of a Digital Lock Nov. 15
    Nov. 29& Dec. 2; Dec. 6& 9 [part 2]. Lab 9: Final Project: Electronic Dice Game
    • Datapath and Control Unit
    • Timing issues
    Nov. 29. & Dec. 6
Links



Supported by a grant of Xilinx Corporation 


Back to the ESE200 Homepage Created by Jan Van der Spiegel; August 10, 2000
Updated August 22, 2005.