Purpose

The purpose of this lab is:

• 1. To design a finite state machine for a digital lock.
• 2. To learn to use HDL or the State Editor to define a finite state machine.
• 3. To implement the finite state machine of the digital lock on a FPGA or CPLD
• 4. Learn practical issues related to timing and testing of a synchronous FSM:
• generating a single synchronous input pulse when pressing a push-button
• synchronization of inputs
• 5. To experimentally check the operation of the lock

You need to design a digital lock that has three input push-buttons: A, B and C. Assume that the buttons cannot be pressed simultaneously (an electromechanical interlock guarantees this). The lock should have the following features:

1. When the combination B-C-A-C has been pressed, a signal UNLOCK is asserted that causes the lock to open.

2. Once the lock is open, one can close the lock by pressing any key.

3. To reset the lock to its initial state one can press the sequence A-A from any state, except the alarm state or the reset state.

4.  In order to prevent tampering with the lock, an ALARM will go off  after pressing a wrong button. However, in order to make it harder to figure out the right sequence, we don't want the alarm to go off after the first wrong button has been pressed. Instead, the alarm should go off after pressing 4 buttons, as long as one of the 4 buttons pressed is a wrong one (e.g. the sequences B-C-B-A, A-B-C-A, C-C-B-A, A-A-B-C, etc. would trigger the alarm).

5. The only way to get out of the alarm state is by pressing the C-A sequence.
 

Task one: Design of the Digital Lock FSM.
 

1. Make sure you understand the behavioral description of the project. As with any project specifications not all possibilities may be covered. Feel free to make reasonable assumptions and state them clearly.

2. Draw the state diagram or ASM (Algorithmic State Machine) chart for the digital lock. If you make assumptions because not everything was specified, write them down. Indicate what each state represents, what input conditions cause the state transitions, and what the corresponding outputs are. Number the state S0, S1, etc. The digital lock should have as outputs the UNLOCK and ALARM signals. In order to follow the operation of the FSM during testing, you will also show in the 7-segment display the number of the state that is active. The state that corresponds to the UNLOCK and ALARM situation should be displayed as "U" and "A". It would be great is you could have the "A" blinking to draw the attention that the alarm has been set off. I would suggest to design the state diagram as a Moore machine since that makes the timing easier.

3. After you have derived the state diagram, review the section on "State Editor" , Behavioral Description VHDL or  "State Diagrams" in the ABEL-HDL tutorial.

As part of this task you will be concentrating on implementing and testing your design. This raises some interesting issues which are mainly related to timing. In your design you have assumed that when you press the push-button it will generate a single pulse which is synchronized with the clock. In reality this is not going to be the case unless you take special precautions. We are concerned with three issues:

1. Pulse synchronization
2. Generation of a single pulse when pressing the button.

2. A second problem comes from the fact that when one presses the push-button for a short moment, the time that the switch will be closed is usually much longer (msec range) than one clock period (microseconds or even nanoseconds). As a result, our digital lock (or any other finite state machine) will think that we are supplying a string of ones as the input. Thus, one needs to add a circuit after each push-button switch that will generate only one pulse every time that one presses the push-button, independent of the time one keeps the button pressed. Figure 1 shows the timing diagram.

Figure 1: Timing diagram: signal IN is generated asynchronously while signal X is a pulse that is in sync with the clock signal and lasts for only one clock period.

Notice that in Figure 1 the pulse X is synchronized with the falling edge of the clock. If one uses this pulse as the input to a finite state machine (or FF) that is clocked at the positive clock edge, one has ensured that the set-up and hold times will be respected.

The overall digital lock system is shown in Figure 2. It consists of the core FSM for the lock, together with the debouncing and one-pulse circuit for each push button input. The 7-segment LED is used to display the number of each state or the Alarm (A) and Unlock (U) states.
 
 

Design a circuit that generates a single pulse independent of the length of the input signal IN. You can assume that the clock period is much shorter than the time the input signal IN is asserted high. There are different methods to design such a circuit. One is an ad-hoc method where you are using your experience with flip-flops to come up with the circuit. An alternative method is more systematic and makes use of finite state machine design method. Indeed, the circuit we need to come up with can be considered as a finite state machine with one input and one output. In case you prefer the last method, you should give the state diagram, (or ASM), the transition table, the next state logic (assuming that you are using D flip-flops) and the schematic (flip-flops and gates). Notice that this circuit also takes care of the synchronization problem discussed above.

In summary, you need to design the following circuits as part of the pre-lab:

• State Diagram for the digital lock
• Circuit (schematic with D flip-flops) that generates a single pulse from an push-button signal.

In-lab assignment:
 

A. Parts and Equipment:

• 1. PC
• 2. Xilinx Foundation Tools  F2.1i
• 3. Digilab board or the Xilinx FPGA Demoboard (with XChecker cable and AC Adapter), XS40 or XS95 boards.
• 4. Three push-button switches and protoboard (only when using the FPGA demoboard or the XS40 and XS95 boards).

The goal is to implement, download, display and test the digital lock whose block diagram is shown in Figure 2. During the first task you will design and simulate  the finite state machines of  the digital lock and the synchronization (one-pulse) circuit. You will also design and simulate the debouncing circuit. As part of the second task, you will complete the top level schematic, simulate, and debug the overall circuit. Finally, you need to compile (implement) and download the  circuit on an FPGA or CPLD and test its operation. A demo needs to be given to the lab instructors..

Task one: Design of the digital lock FSM and a one-pulse circuit.

1. Create a new project called DigLock in the Schematic Flow mode.  Place it in your folder in the user directory on the C: drive.

2. Design the Finite State machine for the digital lock using the State Editor, or by writing  the HDL code based on the state diagram or algorithmic state machine you derived as part of the pre-lab.

• You can design this finite state machine as a Mealy or Moore machine.  In general, the timing is less critical in a Moore machine than in a Mealy machine. It is suggested to use a Moore machine. In case you are using a Mealy machine, read the  example to know when the outputs are valid.

To use the State Editor, go to TOOLS -> DESIGN ENTRY -> STATE EDITOR in the Project Manager window or in the Schematic Editor window, select TOOLS - > DESIGN WIZARD. Follow the guidelines of the State Editor tutorial. For the Contents select select: State Diagram; for the Language select: VHDL. To define the output when in a state for a MOORE machine, make sure to use the "State Action" instead of the "Entry Action". The Entry Action will produce an output at the clock edge when entering a state and go to zero at the next clock pulse. That is usually not what you want. Using the State Action to define the outputs will prevent this problem.
• When done you can synthesize the FSM:
• Go to FSM -> MACHINE - Sreg0; select binary encoding.
• Check the syntax and synthesize the code by going to the SYNTHESIS->CHECK SYNTAX and ->SYNTHESIZE, respectively. Correct any errors if necessary.
• If errors occur, carefully read the Reports by clicking on the Report icon on the top tool bar. Also read the section on "Most common mistakes".
• As you  will need to add some additional circuits to synchronize the inputs later, it is recommended that you make a macro from this Finite State Machine. Go to the PROJECT->CREATE MACRO. Call the macro DLCKFSM (never use more than 8 characters).


3. Simulate the macro to verify the proper operation of the digital lock.

• Assign keystrokes to the input signals and the reset signal. The clock can be connected to the Bc0 output of the binary counter. To make the simulation realistic, make the pulse width of the input signal the same as the clock period. Go to the OPTIONS->SIMULATOR STEP menu and make the single step equal to the period of the clock (e.g. 10ns).
• Toggle the input signal and click on the STEP button in the Simulator window. Repeat this for any required sequence of input signals.
• If the simulator indicated erroneous operation, go back to State Diagram or the HDL code and identify the possible source for the error.
• A convenient way to follow the operation of the FSM and to find out where the circuit goes wrong, is to use the graphical simulation  feature of the FSM. The state diagram will indicate which state is active.
• When the simulation is successful, make a screen capture of the timing diagram that contains the right sequence.

4. Create the FSM for the one-pulse circuit.
• Create a macro for the finite state machine that generates a single pulse (one-pulse) when the input is asserted (see pre-lab). Call this macro "onepulse"
• Simulate the "onepulse" macro.

1. Complete the top level schematic for the digital lock  according to the overall block diagram of Figure 2.
• The ALARM and UNLOCK signals need to have their own outputs. In addition, the output buffers and pads for the 7-segment display are needed.
• You may have to add a switching circuit for the 7-segment LEDs in case you have more than 10 states (when  you are using the Digilab board).
• You still have to add a clock. The easiest way is to use the on-chip clock oscillator OSC4 which is available on the FPGAs (not on the CPLDs). Place the symbol (OSC4) for the oscillator on the schematic. This oscillator has four outputs corresponding to four different clock frequencies. Select the lowest frequency output (i.e. the 490 Hz output) and connect it to the clock inputs of the D flip-flops. In case you are using a CPLD, you need to supply an input pin for an external clock signal.


2. Simulate the top level schematic and verify that the overall circuit works properly. Debug if necessary.

3. When successful, take a screen capture of the functional simulation illustrating the proper operation.

1. Implement the circuit.

2. After the translation, you can use the constraint editor to define the pin locations. Alternatively you can place the pin location on the schematic as you did in the first lab.

• The pin locations for the 7- segment LEDs are given in the write-up of the board you are using (Digilab board, FPGA demoboard, XS40 or XS95 boards).
• In case you are using the Digilab board or the  FPGA demoboard, you will display the UNLOCK and ALARM signals on the  LEDs. The XS40 and XS95 boards don't have these LEDs available. You can use an external LED with a series resistor (330 Ohm).
• The Reset signal has to be supplied. In case you use the Digilab use one of the push button switches (e.g. BTN4). For the FPGA demoboard, use one of the general purpose switches (SW-3).  For the XS40 and XS95 board, you can use an external switch or the parallel port to supply the reset signal.
• Pins for the push-button switches:
• If you are using the Digilab board, you will use three of the four available push buttons BTN on the board.

When using the FPGA demoboard, the XS40 or XS95 boards you will add extrenal push buttons:   A, B and C are generated from three push-button switches.
• Find the available pins on the FPGA or CPLD  chips, corresponding to the board you are using. See the board descriptions for the pin numbers (Digilab, demoboard, XS40 and XS95). For the FPGA demoboard, use the general I/Os. For the XS40 and XS95 board you can use the pins which are connected to  the address lines of the on-board SRAM, since you will not be using the SRAM in this lab.


3. When done with the constraint editor, you can invoke the interactive flow engine to implement the circuit using the new constraint file (make sure you are using the right file as explained in the Constraint Editor write-up). Check the Pad report everytime you run the implementation and verify that the pads have been assigned to the right pin numbers.  In case you have difficulties assigning the right pin numbers with the contraint editor, edit the user constraint file).

4. If the implementation was successful, check the Map Report for the device utilization and the Post Layout Timing Report.

5. Download the circuit.

6. Check the operation of the Digital Lock and observe the UNLOCK, ALARM and State signals. Check as many possible key sequences as possible to convince yourself that the lock works properly under all conditions. Check for instance following sequences (write this in your lab notebook and write down the results of the tests).:

• B-C-A-C: UNLOCK; --> Any key: Reset State
• B-A-A: Reset State
• B- B- A- A: Reset State
• A-B-A-A: Reset State
• C-A-A: Reset State
• C-B-A-A: Reset State
• A-B-A-A: Reset State
• B-C-A-A: Reset State
• A-A-C-A: ALARM
• A-B-C-A: ALARM
• B-C-B-A: ALARM -- > C-A: Reset
• B-C-A-B: ALARM; --> A-B-C-C-C-A: Reset
• A-B-C-A: ALARM; --> C-B-B-C-A: Reset


If the system does not work properly check your state diagram and other circuits. Check also the pad reports to make sure that the right pin locations have been assigned.  In case you are using the XS40 board and the system is circulating through different states, this indicates that the pullup resistors were not implemented. Go back to the schematic and check that the pullup resistors have been placed properly between the input pad and the input buffer. Before closing the schematic, go to OPTION -> CREATE NETLIST. Implement the circuit again and download the latest version/revision. When the circuit works successfully, give a demo to the lab instructor.

7. Take a screen capture of the top level schematic, and the schematics or HDL code for each macro.

Hand-in

You must hand in a lab report that contains the following:

1. Course Title, Lab no, Lab title, your name and date.

2. Section on the Pre-lab with answers to all questions.

3. Section on the lab experiment:

a. Brief description of the lab experiment including the goals.

b. Copy of the schematics (screen capture) and HDL source code of each macro (screen capture)

c. Simulation results

d. Summary of the Device utilization and the delays.

e. Discussion of the results indicating that the circuit functions properly.
 

4. Conclusion.

1. M. Mano and C. Kime, "Logic anc Computer Design Fundamentals," 2nd Edition, Prentice Hall, Upper Saddle River, NJ, 2001.
2. R. Katz, "Contemporary Logic Design", Benjamin/Cummings Publ., Reading, MA, 1994.
3. J. F. Wakerly, "Digital Design," 3rd edition, Prentice Hall, Upper Saddle River, NJ, 2000.
4. P. Horowitz and W. Hill, "The Art of Electronics", Cambridge University Press, Cambridge, 1989; p506.
5. XILINX XC4000 FPGA description.

Copyright, 1999 Jan Van der Spiegel; Created by Jan Van der Spiegel; November 14, 1997; Updated November 14, 2001.