Whenever a mistake occurs, read the error messages carefully or consult the reports for an explanation of the error. You will often find some pointers about what went wrong in these reports. To aid you with the debugging, add probes to the schematic so that you can trace back the error.

Do not use names for Projects, Macros or folders which are longer than 8 characters. Xilinx does not give a warning when you use names longer than 8 characters but gives errors during synthesis (ABEL macros), or implementation without explaining what the error is.

If the following list does not explain your errors, consult the Xilinx support page. There is 24 hours online support and worthwhile using:

• Xilinx Support (answers)
• Xilinx University Resource Center

The following list gives the most common mistakes found during the labs.

Contents

General
ABEL-VHDL
Schematic Editor
Synthesis
Simulator
Implementation
User Constraint File
State Editor

1. Filenames in Xilinx: Do not use names of projects, macros or folders which are more than 8 characters long. This could cause unexpected problems such as "Illegal Operation...Must import netlist first." This applies to all names in the full path. In order to call a file, the system uses the full pathname, ex. c:\folder\<projectname>. None of these names should be longer than 8 charatcters!
2. File not found. This may be caused when you copy your project  to another folder without copying the .pdf file. It is important that you always copy both the project folder AND the .pdf file. These should be together. In case you need to copy a project it is advised that you do not copy it using the Windows copy and past facilities but that you copy if within Xilinx. In the Project Manager window, go to FILE -> COPY PROJECT. Select the desired folder and save. This will copy both the project folder and the .pdf file. An even better way is to use the ARCHIVE Feature. This will put both the project folder and .pdf file into a zipped file that you can now copy or even email easily.

1. Not putting the equations in the "Equation section". For instance, putting the equations after the Truth_table section will result in errors and ABEL will not compile.
2. Defining the same output variable twice, once in the Equation section and once in the Truth_table section. This will confuse the system as to what the output is supposed to be.
3. Forgetting to define an output port as an "output" in the direction option or as a registered output 'reg' instead of a combinational output 'com'.
4. The name of an ABEL macro consists of more than 8 characters.
5. After modifying a macro which is used in a top level schematic, one needs to save and update the macro. The same is true for a schematic macro that has been modified. Make sure you synthesize the code and to go to the PROJECT->UPDATE menu (in ABEL) or to UPDATE simulator. A safe way to make sure you are using the updated files is to exit the ABEL-HDL editor before opening the simulator.
6. Typos!!! This may be one of the most common and frustrating errors. Don't be sloppy when typing in the source file; it pays off to give it some extra attention and saves you a lot of debugging time later.
7. Nesting sets definitions. For example, you have defined a set X = [X7..X0] and you need to use this as part of another set, lets say INPUT, which contains the X's as well as another variable Cin. It is a mistake to define INPUT = [Cin, X]. Instead you can define it as follows, INPUT = [Cin, X7..X0]. Such an error will not be flagged during the syntax check but will give unpredictable simulation results.
8. Incorrect use of parentheses. For instance, in the When-Then-Else of If-Then-Else statements when you use multiple equations after the THEN keywork, you need to put these equations between curly braces. Of course, if you are using parentheses, make sure each open parenthesis is matched by a closed one.
9. For finite state machines, you need to define the state machine clock signals with equations (e.g. [Q1,Q0].clk = CLOCK;).

1. If you put symbols too close together they will appear to be connected. This is not the case. You must connect symbols with a wire (blue line). It is best not to place symbols too close so that you will have space to route a wire between them. The Integrity Test will net capture this error. In the simulation it will  probably show up by signals which have a X or Z output.
2. When you name a net using the Name Wire command, you must click carefully on the net (wire) so that the name is attached to that wire. The name should appear in blue. If you don't connect it to a wire, the name will still appear (in green) but it won't be a netname.
3. Don't name different nets with the same name. Each netname has to have a unique name unless they are supposed to be electrically connected. Also do not name the same net with different names. These errors will result in a message "Multiple Drivers Error"
4. Modifying a macro or part of a schematic and not updating the macro or schematic. This can result in incorrect simulations. After changing your schematic, do an UPDATE SIMULATOR and export a netlist. It may also help to close the schematic after you are done with the modifications to make sure it gets updated.
5. When using buses not having the proper correspondence between signals on two buses, one connects (such as connecting the most significant bit to the least significant bit). Be careful how you define your buses and connect them. Pay special attention to the signals when connecting buses.
6. Re-saving your top level schematic under a name of the macro that already exists.
7. Trying to mix "top-level" files. The "top level" schematic (or ABEL file) usually has the same name as your project. Do not change this. A project can have one or more "top level" schematic sheets or design files (ex. PROJECT_NAME1.SCH, PROJECT_NAME2.SCH). However, they have to be of the same type, such as a schematic (.sch) or HDL (X-ABEL or VHDL) but not both. To check what the top-level of the project is, look on the left side of the Project Manager window. Underneath the project's .pdf file you will see .sch files or .ABL files listed.
8. When using a ground or Vcc connection, you should use the GND or VCC symbol from the SC Symbol Library. Do not use the GND symbol that is shown  on the left side tool bar (the second from the bottom)  in the schematic editor.
9. When you get the error of "Bus has multiple drivers" during the implementation, this could indicate that you have more than one top level schematic. For instance, you may have created a macro and kept it as a schematic. You can check this in the Project Manager window. This second schematic may have the same name for buses which will cause a conflict. You should remove any schematic that is not part of the top level one.
10. The schematic shows the logic symbols in light grey. A message saying "Automatic loading of project libraries disabled". This may occur when you add a schematic to a new project. To correct this you can add the libraries to the project:
From the Project Manager:
Select the "File" menu.
Choose "Project Libraries..."
Select "xc4000e" from "Attached Libraries" (or whatever FPGA family you are using).
Choose "ADD"
  "xc4000e" should appear now under the "Project Libraries"

Also, you may need to add the library associated with the schematic you
are adding.  If the name of the schematic you are adding is "FOO.SCH",
then add the library "FOO".

         Select the "File" menu.
                Choose "Project Libraries..."
                Select "FOO" from "Attached Libraries"
                Choose "ADD>>"
                "FOO" should now appear under the "Project Libraries"

Reopen the schematic.
 

1. When trying to synthesize an VHDL file you get the message: "User Break" and the synthesis stops. Or you may also get the message "Another Synthesis process already started". In that case it may help to copy the project (go to the FILE->COPY PROJECT, and give it another name). Restart the Foundation program and open this copied project. If you still get the same error, you may have to delete the following file: s95_syn.lck in the s95_syn.tmp directory. If you don't find the file in the s95_syn.tmp directory, so a search for this file.
2. A macro won't synthesize ( user does not have R/W access). When this happen go to the Tools-Project Libraries-Library
   Manager, then to click on your library and change it from R/O to R/W.
3. Error message: "Not being able to find Intermediate File". This can occur when you synthesize a VHDL macro andthe macro name or any of the directory names that it is stored in are longer than 8 characters.Check the lenght of the macro name and any of the folders in which the project resides. None of the names can have more than 8 characters.

Simulator

Errors with the simulations are often the result of mistakes in the schematic or ABEL source file. See the "Common Mistakes" with ABEL or Schematic.

1. Not updating the netlist or project after making a modification to the schematic or ABEL file before running the simulation. This can result in HiZ outputs in the simulator. A safe way to make sure you are using the updated files is to exit the editor (Schematic or ABEL-HDL editor) after making the modifications. Also exit the simulator and re-open it after making the modifications.
2. Wrong signals when using buses to display the signals. This can be the result of a bus that has been reversed in direction, i.e. the most significant bit becomes the least significant bit, etc. This can be changed by going to SIGNAL->BUS->Change Direction menu.
3. When opening the component selection window (signal selection), no signals appear. This can happen when you just created a new project and defined an ABEL source file. You will need to add the file to the project. In the Project Manager Window go to the DOCUMENT ->ADD menu. Browse until you find the file that has the design you want to simulate. Go back to the simulator; if necessary, restart the simulator.

• You may have modified the schematic and not updated the netlist and simulator. It may help to close the schematic editor and the simulator window first and then opening the simulator again to ensure it uses the latest netlist.
• When different nets have the same name. For instance, you name an input net ANAME and the net after the buffer also ANAME. Although both nets see the same signals, they are physically different nets because the buffer separates them. Nets should have unique names, unless they are supposed to be electrically connected.
• During the timing simulation. The undefined signals may be the result of the synthesis program which often optimize signals (or logic) out. See also Undefined signals in the Timing simulator tutorial.

1. Error signal: Net has multiple connections or multiple drivers. This can be the result of giving the same name to different nets which should not be connected, or by giving a net more than one name. This is also true for buses. To help you find out what is connected to a particular net you can use the Query Window (go to MODE->QUERY or click on the  right icon on the top toolbar) in the Schematic editor. The cursor changes into a question mark. Click on the net of interest and all connection will be shown in the Query window. Check the connections.
2. A macro in the project has the same name as the the top level project (or schematic).
3. Error: "DONE is not HIGH". This error may coccur when the actual device (FPGA) type on the board  is not the same as the one that you specified in the project manager. Check the FPGA on your board and make sure it is the same family and type as the one you specified in the Project manager. If it is different, you can change it. In the Project Manager, go to FILE -> PROJECT TYPE. This will open the Change Project Type Window. Enter the right family of devices and the type. You will have to re-implement the project before downloading the modified version.

1. Typos!!! The user constraint file is case-sensitive. Make sure that the netnames in the .ucf file are exactly the same as on the schematic or in the ABEL file. Don't mix the letter "0" with the letter "O".
2. Forgetting to put "P" in front of the pin number. The pin number must be proceeded by a P as in .... P19;
3. Forgetting the semicolon at the end of a line.
4. Comments should be preceded by a # sign. No semicolon is needed at the end of the comment line.
5. An error message is generated during the Mapping (implementation) related to pin locations. Check that you have specified the right part number and pincount (we are using XC4000E family with 84 pins). This can be done in the Project Manager window, by clicking on the Design Info icon, or from the Design Manager window (go to DESIGN -> IMPLEMENT; in the implement window click on the Part button and select the proper part number).

State Editor

1. When defining the outputs associated with a state in a Moore Machine, do not use the "ENTRY Action" , but use the "STATE Action". The Entry Action will produce an output at the clock edge when entering a state and go to zero at the next clock pulse. That is usually not what you want. Using the State Action to define the outputs will prevent this problem.

Created by Jan Van der Spiegel <jan@ee.upenn.edu>; August 26, 1997; Updated by Jan Van der Spiegel; December 6, 2001.