Contents

• Power supply
• Seven segment LED display
• On board programmable oscillator
• Parallel Port
• SRAM memory
• Microcontroller
• PS/2 mouse and keyboard Port
• VGA Port
• Jumpers
• Checking the board
• References

The XS95 is a convenient board for implementing and experimenting with CPLD designs. The XS95 board contains additional components such as a 8031 microcontroller, SRAM (32 KB for the XS95 and 128 KB for the XS95+ boards), a 100 MHz programmable oscillator, a parallel port, PS/2 port for a mouse or keyboard, and a VGA monitor port. This makes it a convenient system to implement not only CPLD designs but also microcontroller applications where the CPLD is used for low-level signals and the SRAM for data/program storage. The board can be programmed through a parallel port. The CPLD can also be tested using the XSPORT utility that allows you to apply test signals through the parallel port.

The board has a XC95108 CPLD which contains 2,400 usable gates and operates at 5V. It has a breadboard interface that allows you to plug the board into a breadboard so that you can easily access its pins. A schematic diagram of the board is given in Figure 1. The board can be configured for different purposes, such as use in a design environment (default) or use as a stand-alone board, reprogramming the clock, etc. The mode of operation is determined by jumpers. The settings of the jumpers and the correspondent configurations are explained later on in Table 6

.

Notice that the CPLD chip is non-volatile which implies that it can be used by itself without having to re-program it every time the power is switched on.

Power supply

The XS95 board is powered through a 9V DC supply. This can be easily done using a 9V AC adapter (300 mA) which plugs into a 9V DC jack, with a center positive terminal. The board has two voltage regulators that generate the 5V for the CPLD and the rest of the components. The 3.3V and 0V (Ground) are connected to the Vdd and GND pins of the CPLD.

Seven-segment Display

The XS95 board contains one 7-segment LED display whose elements are connected to one of the pins of the CPLD. The pin I/O connections of the display to the CPLD are shown in the table below. A 220W resistor is placed between the LED element and the ground to limit the current needed from the CPLD output. A schematic diagram of the LED circuit used in the display and the numbering of the elements is shown in Figure 2. The LEDs are active-high, which implies that they will light up when a logic "1" is applied to their terminal.

On-board clock

A 100 MHz programmable oscillator is available. The clock is connected to the clock input (GCK1) of the XC95108 CPLD on pin number 9.

The default setting of the clock on the XS95 is 50 MHz. This frequency can be re-programmed by dividing the 100 MHz master clock by any integer from 1 to 2052, resulting in frequencies ranging between 100 MHz and 48.7 KHz.

Programming the clock oscillator

Before reprogramming the oscillator you need to put the oscillator in the programming mode. This is done by placing a shunt on jumper J6 (1-2) (see Figure 1). Do the following steps (exactly in this sequence):

1. Remove the power from the XS95 board
2. Remove the parallel download cable (only after removing the power)
3. Place a shunt on jumper J6 in the set position (on pins 1-2 (Figure 1)
4. Attach the parallel download cable
5. Connect the power cable
6. In the Xstools/bin directory, click on the GXSSETCLK.exe icon. This will open the "XS board divisor frequency" window shown in Figure 3. Select the board type (e.g. XS95-108) and type in the divisor frequency. Leave the External Clock box unchecked. Next, click on the SET button. The frequency divisor is stored in non-volatile memory of the oscillator and does not need to be re-entered when you start up the board unless you want to change the frequency. (NOTE: if you don't have the GSSETCLK program, you can program the oscillator by going to a DOS window and typing the following command:

 

 
 
 
 
 

C:\> XSSETCLK Board_Type Divisor

As an example, in case you want to run the oscillator at 5 MHz (divisor of 20), you would give the following command,

C:\ > XSSETCLK XS95-108 20

7. Repeat steps 1 and 2.
8. Set the shunt on jumper J6 in the osc position (pins 2-3).
9. Re-attach the download and the power cables (in this sequence).

Figure 3: Set XS Board Clock Frequency window

Parallel Port

The XS95 board is programmed through a PC parallel port, using a female DB25 connector on the XS95, labeled J1 in Figure 1. The PC can then transmit signals to the XS95 board for programming the CPLD or testing later on. Communication from the board to the PC is also possible through the status input pins of the PC parallel port.

In case you want to download test signals to the CPLD, this can be done through pins 2 to 9 of the parallel port J1. Table 2 gives the pin numbers of the J1 connector, the corresponding XC95108 pins and the XSPORT arguments. It should be noted that pins 2 and 3 of J1 are connected to an inverting Schmitt-trigger in order to clean up high frequency clock signals through built-in hysteris. This makes the two pins suitable for clock input signals in sequential circuits. If you are using the XSPORT program, you do not need to worry about the inversion since the program accounts for the inversion of these two signals.

SRAM
 

The XS95 boards are equipped with static RAM that can be used to store data for CPLD based designs or can be used in conjunction with the microcontroller to store programs or data. The XS95 has 32 Kbyte while the XS95+ has 128 Kbyte of SRAM. The RAM is organized as a 32K x 8 bit, or 128K x 8 bit memory devices. Connections between the memory and the CPLD and microcontroller are made on the board. A schematic of the memory package and pin names are shown in Fig. 4.

The 32Kbyte and 128Kbye memory has 14 and 16 address pins, respectively. The correspondence between the SRAM pins, the XC95108 and the microcontroller pins are given in Table 3. The Chip Enable (/CE1, /CE2), Output Enable (/OE) and Write Enable (/WE) are active low signals. The /CE2 pin is always connected to the Vdd while, the /CE1 pin is pulled high through a 4.7kW resistor in order to disable the RAM when the CPLD is being configured. This pin is connected to pin 65 of the CPLD and can be driven low when needed. The /OE is driven by the CPLD through pin 62. The /WE signal comes from the microcontroller (Port 3, pin P3.6) and is also connected to pin 63 of the CPLD.

                                                * Only for the XS95+ board with the 128KB SRAM

8031 Microcontroller

A 8031 microcontroller is resident on-board and is powered by the XS95 power supply. Connections to the CPLD and SRAM are made on the board. The INTEL 8031 is a 8-bit controller with, data and program memory, bi-directional and individually addressable I/O lines and full duplex serial port.

The microcontroller multiplexes the eight lower address bits [A0:A7] and the data bits [D0:D7] on port P0 which is connected to both the SRAM data bus and CPLD. Data between the microcontroller and the SRAM is exchanged through this connection. When the lower address bits are present on this port, the microcontroller will generate an ALE signal that latches the address bits in the CPLD which sends them to the lower eight address lines of the SRAM. For the connections between the CPLD, microcontroller and SRAM see Table 3 and Table 4

.

                                                * Only on the SC40+ board with 128KB SRAM

For the 32KB SRAM, the upper 7 memory address bits, [A8:A14] are connected to the Port 2 of the microcontroller, [P2.0:P2:6]. For the board that is populated with an 128 KB SRAM, the memory bits [A8:A15] are connected to Port 2, [P2.0:P2.7], while memory address bit A16 is connected to pin 74 of the CPLD. Port 2 is also connected to the CPLD so that it can decode the address. For a more complete description of the microcontroller connection, consult the XS95 user manual [1].

PS/2 Mouse or Keyboard connector J5

The XS95 board has a connector (J5 in Figure 1) that accepts inputs from a keyboard or a mouse. You will need a keyboard driver circuit that can be downloaded from the XESS homepage, (http://www.xess.com). The Data and Clock lines are connected to port P3.1 and P3.4 of the microcontroller, and to pins 70 and 26 of the CPLD, respectively (see Table 5).

VGA Monitor connector J2

A 15-pin connector (J2) is available to connect a VGA monitor. This can be used to display images on the monitor. In order to do so, you will first need to download a VGA driver circuit to the XS95 board. Examples of drivers are available on the XESS Corp. homepage, (http://www.xess.com). Connections of the VGA port to the CPLD are given in Table 5.

Jumpers

If you are using the board in a normal design environment for downloading a configuration file from a PC through the parallel port, you can leave the default jumper settings. For any other use, select the jumpers settings as explained in Table 6

Testing the XS95 Board

Place the jumpers in the default setting, connect the cable between the PC parallel port and the J1 connector, and power up the board. Go to the XSTOOLS/BIN folder and launch the GXSTEST program. This will open the XS Board test utility, shown in Figure 6. Select the proper board type (ex. XS95-108) and press the TEST button. A message will appear in the window indicating the status of the test. If the test is successful, the LED on the board will display a 0, otherwise an E will be displayed to indicate an error. If an error occurs, check the parallel port connection and verify that the jumpers are in the proper location.

References:

1. XS95, XSP Board V1.3 User Manual, XESS Corp, Apex, NC, 1999 (http://www.xess.com/xs95-manual-v1_3.pdf). This file contains a detailed schematic of the XS95 board.
2. The Practical Xilinx Designer Lab Book, David Van den Bout, Prentice Hall, Upper Saddle River, 1999.
3. The 8051 Cross Assembler User manual, Metalink Corp, Chandler, AZ, 1996 (see also http://www.xess.com/asm51.pdf at the XESS Corp. website)
4. INTEL 80C31/80C51 8-bit Microcontroller Datasheet, INTEL Corp, 1995 (http://apps.intel.com/product_selector/showdetail.asp?prod=N80C31BH%2D12#section1)

Created by Jan Van der Spiegel <jan@ee.upenn.edu>;Updated June 12, 2000.