Purpose

1. To Understand delays in digital circuits
2. To Learn to use the Timing Simulator
3. To Design a 16-bit carry-lookahead adder and measure its delay.

Up to now we have been interested in the functional operation of logic circuits. In the previous labs you used the logic simulator to verify that the circuits function properly. However, there is one other important aspect to circuit design: the speed at which it operates. The speed of a digital circuit is very important, as it will determine the maximum frequency at which it can work. Let us consider a PC that has a clock frequency of 800 MHz. That means that each 1.25 ns (i.e. period T=1/frequency) the PC will perform a computation! As we will see, this will require clever circuit design.

You may ask yourself what determines the speed or the maximum frequency of a digital system? The answer is the delays of the circuits. There are several factors that contribute to the delay. One is the propagation delay due to the internal structure of the gates, another factor is the loading of the output buffers  (due to fanout and net delays), and a third factor is the logic circuit itself.

1. Propagation delay


When the input signal of a gate changes, the output signal will not change instantaneously as is shown in Figure 1 below.
 

Figure 1: Propagation delay of gates
The propagation delay (or gate delay) of a gate is the time difference between the change of the input and output signals. There are two types of gate delays, T_PHL and T_PLH, as indicated in Figure1. The value of the propagation delay varies from gate to gate and from logic family to family. In general the more you are willing to pay for a device (or chip), the faster it will be. The FPGAs we are using in the lab have gate delays which vary between 1.5 and 4.5ns. The actual delay depends on the way the logic gates have been mapped into the LUTs (Look up table) of a CLB (Configurable Logic Block). The I/O buffers have delays in the range of 2-4ns.
 
2. Fanout and net delays

 

 

The propagation delay described above is caused by parasitic capacitors inside the gates and the physical limitations of the devices used to build these gates. Another cause of delay is the capacitor associated with the loads seen by a gate. These capacitors are the result of the wiring (net delays) between gates (e.g. a long metal line connecting two gates on a chip) and the input capacitor of the gates as is shown in Figure 2a.
 
 

Figure 2: (a)Parasitic interconnection capacitors and fanout of a gate; (b) hydraulic equivalent.
 
These capacitors need to be charged or discharged through the gate that drives them (e.g. gate 1 in Figure 2a). The more capacitors that need to be charged or discharged the longer it will take for the output to change. Also, the longer the interconnection, the more resistance the nets will have. The easiest way to visualize this is to use a hydraulic equivalent of a capacitor and a resistor: a bucket filled with water and a narrow pipe, respectively, as shown in Figure 2b. The more buckets connected to the drain (i.e. the input inverter), the longer it will take to empty them. This delay is the result of the fanout of the inverter.
 
3. Delay as a result of circuit topography.

The overall speed of a digital system can be measured on an oscilloscope by comparing the input to the output signals. However, during the design phase, the circuit has not yet been fabricated and therefore, cannot be measured. In that case it is possible to determine the delay of circuits by doing a  Timing Simulation. The advantage of a simulation is that one can also determine the delay of internal nodes of a circuit. This can be very helpful to understand which nodes or paths are the slowest and thus limit the overall speed of the circuits. These paths are called "Critical path". It is important to understand which paths are critical in a circuit so that one can reduce their delay.

The actual delay will depend on how the gates have been implemented in the various LUTs and CLBs. Also, the routing of the signals between the different CLBs determines the overall speed. Thus, one needs first to implement the design so that one can provide the Timing Simulator with the block and routing delay information. The Timing Simulator and the Implementation Tools are described in the tutorials.

Ripple-carry vs. Carry-look-ahead Adders

One type of circuit where the effect of gate delays is particularly clear, is an ADDER. In this lab you will be measuring the delay of different types of adder circuits. The 4-bit adder you designed and implemented in the previous lab is called a ripple-carry adder because the result of an addition of two bits depends on the carry generated by the addition of the previous two bits. Thus, the Sum of the most significant bit is only available after the carry signal has rippled through the adder from the least significant stage to the most significant stage. This can be easily understood if one considers the addition of the two 4-bit words: 1 1 1 1₂ + 0 0 0 1₂, as shown in Figure 3.

Figure 3: Addition of two 4-bit numbers illustrating the generation of the carry-out bit

Figure 4: Ripple-carry adder, illustrating the delay of the carry bit.

C_OUT = C_i+1 = A_i.B_i + (A_i Å B_i).C_i.                        (1)

C_i+1 = G_i + P_i.C_i                                                     (2)

G_i = A_i.B_i                           (3)

are called the Generate and Propagate term, respectively.

Lets assume that the delay through an AND gate is one gate delay and through an XOR gate is two gate delays. Notice that  the Propagate and Generate terms only depend on the input bits and thus will be valid after two and one gate delay, respectively. If one uses the above expression to calculate the carry signals, one does not need to wait for the carry to ripple through all the previous stages to find its proper value. Let’s apply this to a 4-bit adder to make it clear.
 

C₁ = G₀ + P₀.C₀                                                                       (5)
C₂ = G₁ + P₁.C₁ = G₁ + P1.G₀ + P₁.P₀.C₀                               (6)
C₃ = G₂ + P₂.G₁ + P₂.P₁.G₀ + P₂.P₁.P₀.C₀                               (7)
C₄ = G₃ + P₃.G₂ + P₃.P₂.G₁ + P₃P₂.P₁.G₀ + P₃P₂.P₁.P₀.C₀      (8)

S_i = A_i Å B_i Å C_i = P_iÅ C_i.                                                          (9)

The carry-lookahead adder can be broken up in two modules: (1) the Partial Full Adder, PFA, which generates Si, Pi and Gi as defined by equations 3, 4 and 9 above; and (2) the Carry Look-ahead Logic, which generates the carry-out bits according to equations 5 to 8. The 4-bit adder can then be built by using 4 PFAs and the Carry Look-ahead logic block as shown in  Figure 5.

Figure 5: Block diagram of a 4-bit CLA.

        P_G = P₃.P₂.P₁.P₀                          ;                                       (10)

        G_G = G₃ + P₃G₂ + P₃.P₂.G₁. + P₃.P₂.P₁.G₀                         (11)

The group Propagate P_G and Generate G_G will be available after  3 and 4 gate delays, respectively (one or two additional delays than the P_i and G_i signals, respectively).

Figure 6: Block diagram of a 16-bit CLA Adder

1. Describe briefly which factors determine the maximum frequency of a digital circuit.
2. What is a critical path in a digital circuit?
3. Read the tutorial on "Timing Simulation".
4. Assuming that one  delay in a AND and OR gate  is 1 gate delay and in an XOR gate 2 gate delays, determine:

 
1. What is the worst-case delay of the Carry-out of the one-bit Full Adder circuit of Lab 1
2. Consider the 4-bit adder you designed in the previous lab. Under what conditions of input signals does the worst case delay occur for the carry-out signal? What is the worst case delay for the carry-out (of the last stage)?
3. What is the worst case delay of signal S2 of a 4-bit ripply carry adder?
4. What is the worst case delay of signal C2 of a 4-bit ripply carry adder?
5. Assume you add two 16-bit words up using a ripple-carry adder. Considering worst case conditions, after how long a delay will the sum (S) be valid?
6. What is the delay of the Sum bits S0 and S3 of the 4-bit carry-lookahead adder in  figure 5 above?
7. What is the delay of the Sum signals S3 and S15 of the 16-bit CLA in  figure 6 above?
5. Submit your answers online using Blackboard.

A. Parts and Equipment:

1. PC
2. Xilinx Foundation Tools F2.1i

• You will implement  a 16-bit carry-lookahead adder. You will do this by creating a Partial Full Adder (PFA) macro and a Carry-lookahead Logic  macro as shown in Figures  5 and 6.

• Open a new project in your folder (c:\users\your_name\) and call it  MY16CLA.
• Open the schematic editor.
• Create a macro of the PFA using  VHDL. Call the macro MYPFA. When the PFA has been synthesized, do a functional simulation to verify that the circuit works.


NOTE: You can do a functional simulation without having to connect input and output terminals to the macro input. Do the following:

• Go to the simulator by clicking on the SIM icon on the top toolbar.
• In the Waveform viewer, click on the Add Signals icon (or go to SIGNALS -> ADD SIGNALS). In the middle panel of the Component Selection window, called Chip Selection, you will see the name of the macro, MYPFA. Double click on it. In the right panel, Scan Hierarchy, all the input and output pins will be displayed. Select these pins by double clicking. When done, click the Close button.
• Open the stimulator window and define the A and B bits using the Binary counter.
• Do a functional simulation and verify the operation.

• Create a macro for the Carry- Look-Ahead Logic block. Call this MYCLALOG. Use VHDL to create this macro. You should also generate the Groups Generate and Propagate signals, P_G and G_G, respectively. You do not need to create the carry C4. Do a simulation, as explained above.
• Now you can create a 4-bit CLA adder macro. In the schematic editor go to the TOOLS -> SYMBOL WIZARD menu and create the symbol for a Schematic macro, called MY4CLA. Once the symbol has been created, draw the schematic for the 4-bit adder using the above defined modules of PFA and MYCLALOG. The adder should have as input A[3:0], B[3:0], and CIN. The outputs are S[3:0], P_G, and G_G. Be careful when connecting the carry signals. Since this schematic will be used as a macro, you do not need to add input/output buffers and pads. For single signals use a terminal; and for the buses (ex. A, B and S), define the  bus as "input" or "output" bus (or select End Bus if the terminals have been defined already).
• When finished, synthesize the macro and simulate the 4-bit adder. Verify its operation and make a screen caption of the functional simulation waveforms (only one page).
• You are now ready to create the top level schematic of the 16-bit carry-lookahead adder. Use the block diagram of Figure 6.
• The schematic of the 16-bit adder is the top level schematic. All the input pins (A[15:0], B[15:0], CIN, SOUT[15:0], and COUT) need to be connected to pads and buffers. Cout is the last carry of the adder, corresponding to C16 and can be generated from the groups Propagate and Generate signals.
• In order to keep the schematic and its interconnections managable, use buses as much as possible. It may be helpful to use a 16-bit wide bus for input signals A and B. This bus can be split up into segments of 4 bits that each feeds into the 4-bit inputs of each of the 4-bit CLA macros. This can be done by first drawing a 16-bit wide bus (e.g. AIN[15:0]). Then connect the 4-bit wide input bus (e.g. A[3:0]) of the first 4-bit CLA  to the 16-bit wide A bus; next connect the input of the 2nd 4-bit CLA to the same A bus, etc. until all 16 inputs have been connected. Now you need to specify how the bus signals are connected. This can be done by giving the bus segment the proper name by clicking on the bus. This will open the Edit Bus window. Keep the name but change the bus width. For instance, to specify a 4-bit wide bus segment that connects to the input of the first 4-bit adder, give it the name AIN and as width [3:0]. It is important that the name of the bus segment is the same as the name of the 16-bit bus.  Do the same for the other bus segments (e.g. AIN[7:4], etc.). For more information about buses in the Schematic Entry window, select HELP -> SCHEMATIC EDITOR HELP CONTENTS. In the help window select INDEX and type "buses" or "bus connections".

 
• When done, do a functional simulation and verify that the circuit works properly. Instead of defining each input  signal A0, A1 ... A15, B0, B1, ... B15 separately, it is more convenient to use the Formulas to define the input  signals of the input buses. See section on Formulas in the Logic Simulator Tutorial. When the simulation give the right result,  take a screen catpure of the waveforms (again only one page).

 
• When the circuit works properly, you need to implement it so that you can do a timing simulation later on.
• Make sure you added pads and buffers for each input and output. If you don't add pads, the mapping software will remove all the logic between input and output "connectors" and your circuit will have no logic or little logic left!
• Before implementing the design, go to the Program Manager and select the IMPLEMENTATION -> IMPLEMENT DESIGN menu (or ->OPTIONS menu).  In the Implement Design window click on the Option button. When the Options window opens, click on the Edit Options button for the Simulations (Foundation EDIF). In the Simulation Options window, click on the General Tab and De-select the option: Correlate Simulation Data to Input Design. This will prevent that the timing simulation will give undefined signals (see also undefined signals in the timing simulation tutorial).
• For the implementation, see previous lab or check the tutorial on Design Implementation. Use a device speed of 4.
• Check the reports and write the results in your lab notebook:
• Check the Map Report for the device utilization and the equivalent gate count. Check if logic has been removed during the mapping step.
• Check the Post Layout Timing Report. Find the maximum combinational path delay and net delay.Between which input pin and output pin does the maximum delay occur? What is the maximum  frequency at which the input signals can applied without causing erroneous operation of the 16 bit adder?
• Timing simulation (Verification): In the Project Manager click on the Verification (Timing Simulation) icon. This will open the timing simulator. Do a worst-case simulation of the CLA and determine the delay of the Sum bits and the Carry out bit COUT.  In case you have problems with the timing simulation and some of the signals are undefined (gray waveform), see the notes below.  You do not need to go through all the possible input combinations because you have verified that the circuit works properly by doing a functional simulation above.
• Apply input signals A[15:0] and B[15:0] which give a worst case scenario for the delays of the sum and carry-out signals? Measure the delays between the time the input signal is applied and the sum and carry-out signal changes (use the measurement option in the simulator). Write these numbers down in your lab notebook. Do they correspond to the ones reported in the Post Layout Timing report?
• When doing the timing simulation, be careful that the period of the stimuli (i.e. the signals applied to the input) is larger than the longest delay of the circuit. If your input signal is changing before the output signals appear (due to the delay), you will get useless and unpredictible results. You can change the period of the binary counter output (Bc:) by going to the OPTIONS -> PREFERENCES -> SIMULATIONS; adjust the Clock Period of B0 to a value larger than the maximum delay (e.g. 50 ns). The input signal should not change until all the output signals have settled to the proper value.
• Besides the delays of the Sum and Carry signal determine also the delay of the input and output buffers.
• Take a screen capture of the simulation data, including the measurement data for the delays of the Sum, Carry-out and buffer delays (max 2 screens).

•  In case some of the signals show as an undefined signal (gray in the waveform viewer window or blue X on the schematic) make sure that you De-select the option: Correlate Simulation Data to Input Design in the Implementation Options (Simulations) as explained above or in the timing simulation tutorial.
• Use the Measurement tool to determine the delay: go to WAVEFORM -> MEASURMENT -> MEASUREMENT ON. This will allow you to display the delays.

Lab Report including

1. Course title, Lab no, Lab section, your name and date.
2. Section on the lab experiments:

1. Brief description of the lab including the goals
2. Copy of the VHDL source code of the macros PFA, MYCLALOG.
3. Screen capture of the schematic of the 4 bit and 16-bit CLA adders
4. Screen catpure of the funtional simulation of the 4-bit CLA adder (label printouts)
5. Screen catpure of the timing simulation with measurements16-bit carry-look-ahead adders.
6. Summary of the Map (device utilization) and Timing Reports (delays)
7. Discussion of the measured delays using the Timing simulator.
8. Maximum frequency at which the 16 bit CLA adder can be used.

4. Discussion and conclusions.

1. R. Katz, "Contemporary Logic Design", Chapter 3, sections 3.3.1 and 3.3.2; Chapter 5, section 5.2
2. D. Van den Bout, "The Practical Xilinx Designer Lab Book", Prentice Hall, Upper Saddle River, NJ, 1998.
3. J. Wakerly, "Digital Design,"  3rd edition, Prentice Hall, Upper Saddle River, NJ, 2000.
4. M. M. Mano and C. R. Kime, "Logic and Computer Design Fundamentals", 2nd Ed., Prentice Hall, Upper Saddle River, NJ, 2001.