The tutorial contains Basic and Advanced modules. You can complete all of the Basic tutorial modules sequentially, by starting with the Design Entry module, or you can choose to complete any of the Basic or Advanced modules independantly or non-sequentially.
To start a tutorial module, click a module button in the navigation bar, or select a module from one of the following two tables:
Basic Tutorial Modules | |
Module | Description |
Design Entry |
Teaches you how to create a top-level Block Design File (.bdf) with the Block Editor. You also create several lower-level Verilog HDL Design Files (.v) using the Text Editor and the MegaWizard® Plug-In Manager. |
Compilation |
Teaches you how to compile a design using Compiler settings to control compilation processing. You also learn how to view the floorplan that shows how the Compiler placed logic in the device and how to make resource and logic option assignments. |
Timing Analysis |
Teaches you how to analyze the timing performance of logic in a design, including how to specify timing requirements and how to perform multiclock timing analysis. |
Simulation |
Teaches you how to create a Vector Waveform File (.vwf) that contains input vectors for timing simulation and how to create Simulator settings that control simulation processing. You also learn how to perform a timing simulation. |
Programming |
Teaches you how to use the Quartus II Programmer to configure an Altera device. |
Advanced Tutorial Modules | |
Module | Description |
Excalibur |
Teaches you how to create and instantiate an ARM-based Excalibur embedded processor megafunction in a design. You also learn how to perform a functional simulation in the Quartus II software and how to build software code to run on the Excalibur embedded processor core. |
LogicLock |
Teaches you how to optimize a specific logic block and how to preserve the optimized constraints with the LogicLock feature of the Quartus II software. You also learn how to import the optimized block into the top-level design. |
Stratix |
Teaches you how to use some of the unique features of the Stratix device family, including TriMatrix memory, High-speed LVDS, and DSP blocks. You also learn how the Compiler implements the design in a Stratix device by examining the compiled design. |