Design Entry Module

In the Quartus II software, a "project" consists of the complete set of design files, assignment files, simulation files, system settings, and hierarchy information for a design. The Design Entry tutorial module guides you through the steps needed to create the fir_filter tutorial project, and then explains how to create a top-level Block Design File (.bdf) that contains blocks representing the lower-level design files. Next, you create the lower-level Verilog Design Files (.v) that these blocks represent. You complete the Design Entry module by creating a custom megafunction variation that is instantiated by one of the lower-level design files. The project you create in this module demonstrates top-down design methodology.