Compilation Module |
The Quartus II Compiler consists of a series of modules that check the design for errors, synthesize the logic, fit the design into an Altera device, and generate output files for simulation, timing analysis, and device programming.
The Compiler first extracts information that defines the hierarchical connections between a project's design files and checks the designs for basic design entry errors. Then, it creates an organizational map of the design and combines all design files into a flattened database that can be processed efficiently.
You can instruct the Compiler to apply a variety of techniques, such as timing-driven compilation, to increase the speed of your design and optimize the device resource usage. Both during and after compilation, you can view the results in the Compilation Report window. The Compiler also creates programming files that the Quartus II Programmer or another industry-standard programmer can use to program or configure an Altera device.
The Compilation tutorial module guides you through the steps necessary to specify Compiler settings, create a resource assignment, compile the top-level design entity, view the fit in the Last Compilation floorplan, assign logic to an Embedded System Block (ESB), and recompile the design.
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