Timing Analysis Module

With the Quartus II Timing Analyzer, you can analyze the timing performance of all logic in your design. You can trace signal paths and locate them in the Floorplan Editor, determining critical speed paths that limit the design's performance.

The Quartus II Timing Analyzer runs automatically at the end of the compilation process, or you can run the Timing Analyzer separately after first-time project compilation. When timing analysis is complete, timing information is reported in the Timing Analyses folder of the Compilation Report.

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The Timing Analysis tutorial module guides you through the steps necessary to view the timing analysis results in the Compilation Report window, specify timing requirements, perform multiclock timing analysis, and assign a multicycle path.

If you did not sequentially complete the Design Entry and Compilation tutorial modules before starting this module, open and compile the timing analysis project. If you already sequentially completed the Design Entry and Compilation tutorial modules, proceed to Section 1: View Timing Analysis Results.