ARM-Based Excalibur Module

The ARM^®-based Excalibur^™ device family is based on system-on-a-programmable-chip (SOPC) architecture, consisting of an ARM-based Excalibur embedded processor stripe and an APEX^™ 20KE programmable logic device (PLD). The stripe contains the ARM processor core, peripherals, and a memory subsystem. This architecture allows the stripe and programmable logic device to be optimized for performance, enabling maximum integration and system cost reductions.

This tutorial guides you through the steps necessary to create and instantiate an ARM-based Excalibur processor megafunction in a design, perform a functional simulation in the Quartus II software, build software code to run on the ARM-based Excalibur embedded processor core, and program an Excalibur device.

This tutorial assumes you have installed the Altera ARM Developer Suite (ADS) version 1.1 to the c:\program files\arm\adsv1_1\ directory. If you installed ADS in a different drive and/or directory, substitute the appropriate drive and/or directory name when completing this tutorial. In addition, this Advanced tutorial module assumes that you are familiar with the basic functionality of the Quartus II software, as described in the Basic tutorial modules.