Verilog HDL

Implementing CAM, RAM & ROM

The Quartus® II software and Verilog HDL support several library of parameterized modules (LPM) functions and other megafunctions that allow you to implement content-addressable memory (CAM), RAM, and ROM in Altera® devices. The generic, scalable nature of each of these functions ensures that you can use them to implement any supported type of CAM, RAM, or ROM.

NOTE

  1. Altera recommends that you either use Altera-provided megafunctions to implement CAM, RAM, or ROM, or use the MegaWizard® Plug-In Manager (Tools menu) to edit Altera-provided CAM, RAM, or ROM megafunctions. You should not create a megafunction to implement memory or edit the text file for an Altera-provided megafunction.

  2. The Quartus II software can also infer RAM from a suitable description in a Verilog Design File (.v). See Implementing Inferred RAM for more information.

You can use the following megafunctions to implement CAM, RAM, and ROM in the Quartus II software:

Name: Description:
lpm_ram_dq Synchronous or asynchronous memory with separate input and output ports
lpm_ram_io Synchronous or asynchronous memory with a single I/O port
lpm_rom Synchronous or asynchronous read-only memory
altsyncram True dual-port memory
lpm_ram_dp Dual-port memory
altdpram Dual-port memory
altqpram Quad-port memory
lpm_fifo_dc Dual-clock first-in first-out (FIFO) buffer
lpm_fifo+ Single-clock FIFO buffer
altcam Content-addressable memory (CAM)

In these logic functions, parameters are used to determine the input and output data widths; the number of data words stored in memory; whether data inputs, address inputs, control inputs, and outputs are registered or unregistered; whether an initial memory content file should be included for a RAM block; and so on. You must declare parameter names and values for an instance of a CAM, RAM, or ROM logic function using Defparam Statements, as described in Using Parameterized Functions.

NOTE You must have a Defparam Statement for each required parameter in the logic function instance; however, you can allow the Quartus II software to use default values for optional parameters, as described in Parameter Value Search Order.

The example below shows ram256x8.v, a Verilog Design File (.v) for a 256 x 8-bit lpm_ram_dq function with separate input and output ports.

module ram256x8 (data, address, we, inclock, outclock, q);

    input   [7:0]data; 
    input   [7:0]address;
    input   we, inclock, outclock;
    output  [7:0]q;

    lpm_ram_dq inst_1 (.q (q), .data (data), .address (address),
                       .we (we), .inclock (inclock),
                       .outclock (outclock));

        defparam inst_1.lpm_width = 8;
        defparam inst_1.lpm_widthad = 8;
     
endmodule

The lpm_ram_dq instance includes two Defparam Statements that assign values to the lpm_width and lpm_widthad parameters for the instance. These parameters are defined in the WITH clause of the AHDL Function Prototype for the lpm_ram_dq function. (The Help topic describing a Quartus II parameterized function shows the Function Prototype for that function.)

For more information, see the following sections of the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual:


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