Megafunction

lpm_ram_io (RAM) Megafunction

Parameterized RAM with a single I/O port megafunction. This megafunction is provided only for backward compatibility in Cyclone™, Stratix™, and Stratix™ GX designs; instead, Altera® recommends using the altsyncram megafunction. The lpm_ram_io function uses Embedded System Blocks (ESB) in APEX™ 20K, APEX™ II, ARM®-based Excalibur™, and Mercury™ devices, Embedded Array Blocks (EAB) in ACEX® 1K and FLEX 10KE devices, or DFFE primitives or latch arrays in FLEX® 6000, MAX® 3000, and MAX 7000 devices or if the USE_EAB parameter set to "OFF". Altera strongly recommends using synchronous rather than asynchronous RAM functions.

NOTE The Quartus® II Compiler automatically implements suitable portions of this function in ESBs in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, and in EABs in ACEX 1K and FLEX 10KE devices. The Compiler automatically implements this function in logic cells in FLEX 6000, MAX 3000, and MAX 7000 devices.

Altera recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_ram_io (address[LPM_WIDTHAD-1..0], we, inclock, outclock, outenab, memenab)
   WITH (LPM_WIDTH, LPM_WIDTHAD, LPM_NUMWORDS, LPM_FILE, LPM_INDATA, LPM_ADDRESS_CONTROL, LPM_OUTDATA)
   RETURNS (dio[LPM_WIDTH-1..0]);

 

VHDL Component Declaration:

 
COMPONENT lpm_ram_io
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_WIDTHAD: POSITIVE;
      LPM_NUMWORDS: NATURAL := 0;
      LPM_INDATA: STRING := "REGISTERED";
      LPM_ADDRESS_CONTROL: STRING := "REGISTERED";
      LPM_OUTDATA: STRING := "REGISTERED";
      LPM_FILE: STRING; := "UNUSED"
      LPM_TYPE: STRING := "LPM_RAM_IO";
      LPM_HINT: STRING := "UNUSED");
   PORT (address: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
      inclock, outclock: IN STD_LOGIC := '0';
      memenab, outenab : IN STD_LOGIC := '1';
      we: IN STD_LOGIC;
      dio: INOUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
address[] Yes Address input to the memory. Input port LPM_WIDTHAD wide. If memenab is used, it should be inactive when address[] is changing.
we Yes Write Enable input. Enables write operations to the memory when high. If no Clock ports are used, the data on the address[] port should not change when we is high (1). Required if clock is not present.
inclock No Synchronizes loading memory. If the inclock port is used, the we port acts as an enable for write operations synchronized to the rising edge of the inclock signal. If the inclock port is not used, the we port acts as an enable for asynchronous write operations.
outclock No Synchronizes dio[] from memory. The addressed memory content-to-q[] response is synchronous when the outclock port is connected, and asynchronous when it is not connected.
memenab No Memory output tri-state enable. Either memenab or outenab must be connected. If memenab is present, it should be inactive when address[] is changing. This port is available for backward compatibility only and Altera recommends that you not use this port.
outenab No Output Enable input. High (1): dio from Memory [address] Low (0): Memory [address] from dio. Either memenab or outenab must be present.

BIDIRECTIONAL PORTS

Port Name Required Description Comments
dio[] Yes Bidirectional data port for the memory. Bidirectional port LPM_WIDTH wide.

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of dio[] and internal data and q ports.
LPM_WIDTHAD Integer Yes Width of the address port. LPM_WIDTHAD should be (but is not required to be) equal to LOG2(LPM_NUMWORDS). If LPM_WIDTHAD is too small, some memory locations will not be addressable. If it is too large, the addresses that are too high will return undefined (X) logic levels.
LPM_NUMWORDS Integer No Number of words stored in memory. In general, this value should be (but is not required to be) 2 ^ LPM_WIDTHAD-1 < LPM_NUMWORDS <= 2 ^ LPM_WIDTHAD. If omitted, the default is 2 ^ LPM_WIDTHAD.
LPM_FILE String No Name of the Memory Initialization File (.mif) or Hexadecimal (Intel-Format) Output File (.hexout) containing ROM initialization data ("<file name>"), or "UNUSED". If omitted, contents default to all 0s. The we port must be registered to support memory initialization.
LPM_INDATA String No Values are "REGISTERED", "UNREGISTERED", and "UNUSED". Controls whether the data port is registered. If omitted, the default is "REGISTERED".
LPM_ADDRESS_CONTROL String No Values are "REGISTERED", "UNREGISTERED", and "UNUSED". Controls whether the address[], memenab, and we ports are registered. If omitted, the default is "REGISTERED".
LPM_OUTDATA String No Values are "REGISTERED", "UNREGISTERED", and "UNUSED". Controls whether the dio[] port is registered. If omitted, the default is "REGISTERED".
LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.
USE_EAB String No

Altera-specific parameter. Values are "ON", "OFF", and "UNUSED". Setting the USE_EAB parameter to OFF prevents the Quartus II software from using ESBs to implement the logic in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, or EABs in ACEX 1K and FLEX 10KE devices; it can only use flipflops or latches. (The "ON" setting is not useful in memory functions: the Quartus II software automatically implements memory functions in ESBs or EABs by default.) This parameter is not available for simulation with other EDA simulators and for FLEX 6000, MAX 3000, and MAX 7000 devices.

If you wish to use this parameter when you instantiate the function in a Block Design File (.bdf), you must specify it by entering the parameter name and value manually with the Parameters tab (Symbol Properties Command) or the Parameters tab (Block Properties Command). You can also use this parameter name in a Text Design File (.tdf) or a Verilog Design File (.v). You must use the LPM_HINT parameter to specify the USE_EAB parameter in VHDL Design Files.

 

Truth Table/Functionality:
Synchronous Read or Write to Memory (all inputs registered)
inclock we outenab Function
Rising Edge L L High impedance (output not enabled).
Rising Edge X H The memory location pointed to by address[] is read to dio[].
Rising Edge H L dio[] is written to the memory location pointed to by address[].

For devices with ESBs or EABs, the lpm_ram_io megafunction internally writes the data to memory while the write clock is low.


Synchronous Read from Memory
outclock we outenab Function Note (9)
Rising Edge L H The output register is loaded with the contents of the memory location pointed to by address. dio[] outputs the contents of the output register.
notRising Edge L H No change. dio[] is held constant until the next clock. Data changes on next outclock.

Totally asynchronous memory operations occur when neither inclock nor outclock is connected. The output q is asynchronous and reflects the data in the memory location pointed to by address[].

Asynchronous Memory Operations
we outenab Function Note (9)
L L High impedance (output not enabled).
X H No change (No we).
H L dio[] is written to the memory location pointed to by address[]. The address[] port should not change while we is high (outenab is low). If the data on the address[] port changes while we is high (outenab is low), all memory locations that are addressed are overwritten with dio.

 

Resource Usage:

Uses one embedded cell per data output bit for ACEX 1K, APEX 20K, APEX II, ARM-based Excalibur, FLEX 10KE, and Mercury devices; however, in FLEX 6000, MAX 3000, and MAX 7000 devices, or if the USE_EAB parameter is set to "OFF", uses one logic cell per memory bit.

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