See Also

Parameterized true dual-port RAM megafunction. The altsyncram megafunction is available for Cyclone^™, Stratix^™, and Stratix^™ GX devices only.

Altera^® recommends instantiating this function as described in Using the MegaWizard^® Plug-In Manager (Tools menu).

This topic contains the following information:

• AHDL Function Prototype (also applies to Verilog HDL)
• VHDL Component Declaration
• VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
• Port Descriptions
• Parameter Descriptions

FUNCTION altsyncram (wren_a, wren_b, data_a[OPERATION_MODE != "ROM" ? WIDTH_A - 1 
      : 0..0], data_b[(OPERATION_MODE == "BIDIR_DUAL_PORT") ? WIDTH_B - 1 : 0..0], 
      address_a[WIDTHAD_A - 1..0], address_b[(OPERATION_MODE == "BIDIR_DUAL_PORT" 
      # OPERATION_MODE== "DUAL_PORT") ? WIDTHAD_B - 1 : 0..0], clock0, clock1, clocken0,
      clocken1, rden_b, aclr0, aclr1, byteena_a[OPERATION_MODE != "ROM" ? ((WIDTH_A 
      > 15) ? ((WIDTH_BYTEENA_A > 1 ? WIDTH_BYTEENA_A-1 : 0)) : 0 ): 0..0], 
      byteena_b[OPERATION_MODE == "BIDIR_DUAL_PORT" ? ((WIDTH_B > 15)?
      (WIDTH_BYTEENA_B > 1 ? WIDTH_BYTEENA_B-1 : 0) : 0 ): 0..0] )
   WITH ( OPERATION_MODE, WIDTH_A, WIDTHAD_A, NUMWORDS_A, INDATA_ACLR_A, WRCONTROL_ACLR_A,
      ADDRESS_ACLR_A, WIDTH_B, WIDTHAD_B, NUMWORDS_B, INDATA_REG_B, INDATA_ACLR_B, 
      WRCONTROL_WRADDRESS_REG_B, WRCONTROL_ACLR_B, ADDRESS_ACLR_B, OUTDATA_REG_A, 
      OUTDATA_ACLR_A, BYTEENA_ACLR_A, RDCONTROL_REG_B, RDCONTROL_ACLR_B, ADDRESS_REG_B,
      OUTDATA_REG_B, OUTDATA_ACLR_B, BYTEENA_REG_B, BYTEENA_ACLR_B, INIT_FILE, 
      INIT_FILE_LAYOUT, MAXIMUM_DEPTH, WIDTH_BYTEENA_A, WIDTH_BYTEENA_B, BYTE_SIZE,
      READ_DURING_WRITE_MODE_MIXED_PORTS, RAM_BLOCK_TYPE)
   RETURNS (q_a[WIDTH_A - 1..0], q_b[(OPERATION_MODE == "DUAL_PORT" # OPERATION_MODE 
      == "BIDIR_DUAL_PORT") ? WIDTH_B - 1 : 0..0] );

COMPONENT altsyncram 
   GENERIC 
      (OPERATION_MODE                    :  STRING  := "SINGLE_PORT";    -- "BIDIR_DUAL_PORT";
      WIDTH_A                            :  INTEGER := 8;    -- 1;
      WIDTHAD_A                          :  INTEGER := 2;    -- 1;
      NUMWORDS_A                         :  INTEGER := 4;    -- 1;
      OUTDATA_REG_A                      :  STRING  := "UNREGISTERED";
      ADDRESS_ACLR_A                     :  STRING  := "NONE";
      OUTDATA_ACLR_A                     :  STRING  := "NONE";
      INDATA_ACLR_A                      :  STRING  := "NONE";
      WRCONTROL_ACLR_A                   :  STRING  := "NONE";
      BYTEENA_ACLR_A                     :  STRING  := "NONE";
      WIDTH_BYTEENA_A                    :  INTEGER := 1;
      WIDTH_B                            :  INTEGER := 8;    -- 1;
      WIDTHAD_B                          :  INTEGER := 4;    -- 1;
      NUMWORDS_B                         :  INTEGER := 4;    -- 1;
      RDCONTROL_REG_B                    :  STRING  := "CLOCK1";
      ADDRESS_REG_B                      :  STRING  := "CLOCK1";
      INDATA_REG_B                       :  STRING  := "CLOCK1";
      WRCONTROL_WRADDRESS_REG_B          :  STRING  := "CLOCK1";
      BYTEENA_REG_B                      :  STRING  := "CLOCK1";
      OUTDATA_REG_B                      :  STRING  := "UNREGISTERED";
      OUTDATA_ACLR_B                     :  STRING  := "NONE";
      RDCONTROL_ACLR_B                   :  STRING  := "NONE";
      INDATA_ACLR_B                      :  STRING  := "NONE";
      WRCONTROL_ACLR_B                   :  STRING  := "NONE";
      ADDRESS_ACLR_B                     :  STRING  := "NONE";
      BYTEENA_ACLR_B                     :  STRING  := "NONE";
      WIDTH_BYTEENA_B                    :  INTEGER := 1;
      BYTE_SIZE                          :  INTEGER := 8;
      READ_DURING_WRITE_MODE_MIXED_PORTS :  STRING  := "DONT_CARE";    
      RAM_BLOCK_TYPE                     :  STRING  := "AUTO";    
      INIT_FILE                          :  STRING  := "UNUSED";    
      INIT_FILE_LAYOUT                   :  STRING  := "PORT_A";    
      MAXIMUM_DEPTH                      :  INTEGER := 0;    
      INTENDED_DEVICE_FAMILY             :  STRING  := "STRATIX";
      LPM_HINT                           :  STRING  := "BOGUS");

   PORT (wren_a, wren_b, aclr0, : IN STD_LOGIC := '0';   
           aclr1
        rden_b, clock0, clock1, : IN STD_LOGIC := '1';   
           clocken0, locken1
        data_a                  : IN STD_LOGIC_VECTOR(WIDTH_A - 1 DOWNTO 0):= (OTHERS => '0');
        data_b                  : IN STD_LOGIC_VECTOR(WIDTH_B - 1 DOWNTO 0):= (OTHERS => '0');
        address_a               : IN STD_LOGIC_VECTOR(WIDTHAD_A - 1 DOWNTO 0) := (OTHERS => '0');
        address_b               : IN STD_LOGIC_VECTOR(WIDTHAD_B - 1 DOWNTO 0) := (OTHERS => '0');
        byteena_a               : IN STD_LOGIC_VECTOR( (WIDTH_BYTEENA_A  - 1) DOWNTO 0) := (OTHERS => '1');
        byteena_b               : IN STD_LOGIC_VECTOR( (WIDTH_BYTEENA_B  - 1) DOWNTO 0) := (OTHERS => '1');
        q_a                     : OUT STD_LOGIC_VECTOR(WIDTH_A - 1 DOWNTO 0);
        q_b                     : OUT STD_LOGIC_VECTOR(WIDTH_B - 1 DOWNTO 0));

END COMPONENT; 

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

INPUT PORTS

OUTPUT PORTS

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