Megafunction

lpm_rom (ROM) Megafunction

Parameterized ROM megafunction. Altera® recommends that you use the lpm_rom function to implement all ROM functions. This megafunction is provided only for backward compatibility in Cyclone™, Stratix™, and Stratix™ GX designs; instead, Altera recommends using the altsyncram megafunction. This option is available for all Altera devices supported by the Quartus® II software except MAX® 3000 and MAX 7000 devices.

NOTE The Quartus II Compiler automatically implements suitable portions of this function in Embedded System Blocks (ESB) in APEX™ 20K, APEX™ II, ARM®-based Excalibur™, and Mercury™ devices, and in Embedded Array Blocks (EAB) in ACEX® 1K and FLEX 10KE devices. The Compiler automatically implements this function in logic cells in FLEX® 6000 devices. Therefore, it is not necessary to use the Auto Implement in ROM logic option for this function, and doing so may cause warning messages to appear.

Altera also recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_rom (address[LPM_WIDTHAD-1..0], inclock, outclock, memenab)
   WITH (LPM_WIDTH, LPM_WIDTHAD, LPM_NUMWORDS, LPM_FILE, LPM_ADDRESS_CONTROL, LPM_OUTDATA)
   RETURNS (q[LPM_WIDTH-1..0]);

 

VHDL Component Declaration:

 
COMPONENT lpm_rom
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_WIDTHAD: POSITIVE;
      LPM_NUMWORDS: NATURAL := 0;
      LPM_ADDRESS_CONTROL: STRING := "REGISTERED";
      LPM_OUTDATA: STRING := "REGISTERED";
      LPM_FILE: STRING;
      LPM_TYPE: STRING := "LPM_ROM";
      LPM_HINT: STRING := "UNUSED");
   PORT (address: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
      inclock, outclock: IN STD_LOGIC := '0';
      memenab: IN STD_LOGIC := '1';
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
address[] Yes Address input to the memory. Input port LPM_WIDTHAD wide.
inclock No Clock for input registers. The address[] port is synchronous (registered) when the inclock port is connected, and is asynchronous (unregistered) when the inclock port is not connected.
outclock No Clock for output registers. The addressed memory content-to-q[] response is synchronous when the outclock port is connected, and is asynchronous when it is not connected.
memenab No Memory enable input. High = data output on q[], Low = high-impedance outputs. This port is available for backward compatibility only and Altera recommends that you not use this port.

OUTPUT PORTS

Port Name Required Description Comments
q[] Yes Output of memory. Output port LPM_WIDTH wide.

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of the q[] port.
LPM_WIDTHAD Integer Yes Width of the address[] port. LPM_WIDTHAD should be (but is not required to be) equal to LOG2(LPM_NUMWORDS). If LPM_WIDTHAD is too small, some memory locations will not be addressable. If it is too large, the addresses that are too high will return undefined logic levels.
LPM_NUMWORDS Integer No Number of words stored in memory. In general, this value should be (but is not required to be) 2 ^ LPM_WIDTHAD-1 < LPM_NUMWORDS <= 2 ^ LPM_WIDTHAD. If omitted, the default is 2 ^ LPM_WIDTHAD.
LPM_FILE String Yes Name of the Memory Initialization File (.mif) or Hexadecimal (Intel-Format) Output File (.hexout) containing ROM initialization data ("<file name>"), or "UNUSED".
LPM_ADDRESS_CONTROL String No Values are "REGISTERED", "UNREGISTERED", and "UNUSED". Indicates whether the address port is registered. If omitted, the default is "REGISTERED".
LPM_OUTDATA String No Values are "REGISTERED", "UNREGISTERED", and "UNUSED". Indicates whether the q and eq ports are registered. If omitted, the default is "REGISTERED".
LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.

 

Truth Table/Functionality:
Synchronous Read from Memory
OUTCLOCK Function
notRising Edge No change in output.
Rising Edge The output register is loaded with the contents of the memory location pointed to by address[]. q[] outputs the contents of the output register.

Totally asynchronous memory operations occur when neither inclock nor outclock is connected. The output q[] is asynchronous and reflects the data in the memory location to which address[] points. For asynchronous memory operations the memory location pointed to by address[] is read. Note (9)

 

Resource Usage:

Uses one embedded cell per memory bit; however, in FLEX 6000 devices, uses one logic cell per memory bit.

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