lpm_ram_dq Megafunction

lpm_ram_dq (RAM) Megafunction

Parameterized RAM with separate input and output ports megafunction. Altera^® recommends using lpm_ram_dq to implement asynchronous memory or memory with synchronous inputs and/or outputs. This megafunction is provided only for backward compatibility in Cyclone^™, Stratix^™, and Stratix^™ GX designs; instead, Altera recommends using the altsyncram megafunction. The lpm_ram_dq function uses Embedded System Blocks (ESB) in APEX^™ 20K, APEX^™ II, ARM^®-based Excalibur^™, and Mercury^™ devices, Embedded Array Blocks (EAB) in ACEX^® 1K and FLEX 10KE devices, or DFFE primitives or latch arrays in FLEX^® 6000, MAX^® 3000, and MAX 7000 devices or if the USE_EAB parameter is set to "OFF". Altera strongly recommends using synchronous rather than asynchronous RAM functions.

The Quartus^® II Compiler automatically implements suitable portions of this function in ESBs in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, and in EABs in ACEX 1K and FLEX 10KE devices. The Compiler automatically implements this function in logic cells in FLEX 6000, MAX 3000, and MAX 7000 devices.

Altera also recommends instantiating this function as described in Using the MegaWizard^® Plug-In Manager.

This topic contains the following information:

AHDL Function Prototype (also applies to Verilog HDL)
VHDL Component Declaration
VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
Port Descriptions
Parameter Descriptions
Truth Table/Functionality
Resource Usage

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_ram_dq (data[LPM_WIDTH-1..0], address[LPM_WIDTHAD-1..0], we, inclock, outclock)
   WITH (LPM_WIDTH, LPM_WIDTHAD, LPM_NUMWORDS, LPM_FILE, LPM_INDATA, LPM_ADDRESS_CONTROL, LPM_OUTDATA)
   RETURNS (q[LPM_WIDTH-1..0]);

VHDL Component Declaration:

COMPONENT lpm_ram_dq
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_WIDTHAD: POSITIVE;
      LPM_NUMWORDS: NATURAL := 0;
      LPM_INDATA: STRING := "REGISTERED";
      LPM_ADDRESS_CONTROL: STRING := "REGISTERED";
      LPM_OUTDATA: STRING := "REGISTERED";
      LPM_FILE: STRING := "UNUSED";
      LPM_TYPE: STRING := "LPM_RAM_DQ";
      LPM_HINT: STRING := "UNUSED");
    PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      address: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
      inclock, outclock: IN STD_LOGIC := '0';
      we: IN STD_LOGIC;
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

VHDL LIBRARY-USE Declaration

LIBRARY lpm;
USE lpm.lpm_components.all;

Port Descriptions:

INPUT PORTS

Port Name	Required	Description	Comments
`data[]`	Yes	Data input to the memory.	Input port `LPM_WIDTH` wide.
`address[]`	Yes	Address input to the memory.	Input port `LPM_WIDTHAD` wide.
`we`	Yes	Write enable input. Enables write operations to the memory when high.	Required if `inclock` is not present. If only the `we` port is used, the data on the `address[]` port should not change while we is high. If the data on the `address[]` port changes while the `we` port is high, all memory locations that are addressed are overwritten with `data[]`.
`inclock`	No	Synchronizes memory loading.	If the `inclock` port is used, the `we` port acts as an enable for write operations synchronized to the rising edge of the inclock signal. If the `inclock` port is not used, the `we` port acts as an enable for asynchronous write operations. In addition, if the `inclock` port is not used, the `LPM_INDATA` and `LPM_ADDRESS_CONTROL` parameters should be set to `"UNREGISTERED"`.
`outclock`	No	Synchronizes `q` outputs from memory.	The addressed memory content-to-`q[]` response is synchronous when the `outclock` port is connected, and asynchronous when it is not connected. In addition, if the `outclock` port is not used, the `LPM_OUTDATA` parameter should be set to `"UNREGISTERED"`.

OUTPUT PORTS

Port Name	Required	Description	Comments
`q[]`	Yes	Data output from the memory.	Output port `LPM_WIDTH` wide.

Parameter Descriptions:

Parameter	Type	Required	Description
`LPM_WIDTH`	Integer	Yes	Width of `data[]` and `q[]` ports.
`LPM_WIDTHAD`	Integer	Yes	Width of the `address` port. `LPM_WIDTHAD` should be (but is not required to be) equal to log2(`LPM_NUMWORDS`). If `LPM_WIDTHAD` is too small, some memory locations will not be addressable. If it is too large, the addresses that are too high will return undefined (X) logic levels.
`LPM_NUMWORDS`	Integer	No	Number of words stored in memory. If omitted, the default is 2 ^ `LPM_WIDTHAD`. In general, this value should be (but is not required to be) 2 ^ `LPM_WIDTHAD-`1 < `LPM_NUMWORDS` <= 2 ^ `LPM_WIDTHAD`. If omitted, the default is 2 ^ `LPM_WIDTHAD`.
`LPM_FILE`	String	No	Name of the Memory Initialization File (.mif) or Hexadecimal (Intel-Format) Output File (.hexout) containing ROM initialization data (`"`<file name>`"`), or `"UNUSED"`. If omitted, contents default to all 0s. The `we` port must be registered to support memory initialization.
`LPM_INDATA`	String	No	Values are `"REGISTERED"`, `"UNREGISTERED"`, and `"UNUSED"`. Controls whether the `data` port is registered. If omitted, the default is `"REGISTERED"`. If the `inclock` port is not used, the `LPM_INDATA` and `LPM_ADDRESS_CONTROL` parameters should be set to `"UNREGISTERED"`.
`LPM_ADDRESS_CONTROL`	String	No	Values are `"REGISTERED"`, `"UNREGISTERED"`, and `"UNUSED"`. Controls whether the `address` and `we` ports are registered. If omitted, the default is `"REGISTERED"`. If `LPM_ADDRESS_CONTROL` is `"UNREGISTERED"`, the `we` port is level-sensitive, so that when the `we` port is high, the `address[]` port must be stable to prevent other memory locations from being overwritten. If the `inclock` port is not used, the `LPM_INDATA` and `LPM_ADDRESS_CONTROL`parameters should be set to `"UNREGISTERED"`.
`LPM_OUTDATA`	String	No	Values are `"REGISTERED"`, `"UNREGISTERED"`, and `"UNUSED"`. Controls whether the `q` and internal `eq` ports are registered. If omitted, the default is `"REGISTERED"`. If the `inclock` port is not used, the `LPM_OUTDATA` parameter should be set to `"UNREGISTERED"`.
`LPM_HINT`	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is `"UNUSED"`.
`LPM_TYPE`	String	No	Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.
`USE_EAB`	String	No	Altera-specific parameter. Values are `"ON"`, `"OFF"`, and `"UNUSED"`. Setting the `USE_EAB` parameter to `OFF` prevents the Quartus II software from using ESBs to implement the logic in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, or EABs in ACEX 1K and FLEX 10KE devices; it can only use flipflops or latches. (The `"ON"` setting is not useful in memory functions: the Quartus II software automatically implements memory functions in ESBs or EABs by default.) This parameter is not available for simulation with other EDA simulators and for FLEX 6000, MAX 3000, and MAX 7000 devices. If you wish to use this parameter when you instantiate the function in a Block Design File (.bdf), you must specify it by entering the parameter name and value manually with the Parameters tab (Symbol Properties Command) or the Parameters tab (Block Properties Command). You can also use this parameter name in a Text Design File (.tdf) or a Verilog Design File (.v). You must use the `LPM_HINT` parameter to specify the `USE_EAB` parameter in VHDL Design Files.

Truth Table/Functionality:

Synchronous Read or Write to Memory (all inputs registered)

`inclock`	`we`	Function
not	X	No change (requires rising clock edge).
(write)	H	The memory location pointed to by `address` is loaded with `data`.
(read)	L	The memory location pointed to by `address` is read from the array. If `outclock` is not used, the read data appears at the outputs.

For devices with ESBs or EABs, the lpm_ram_dq megafunction internally writes the data to memory while the write clock is low.

Synchronous Read from Memory

`OUTCLOCK`	Function Note (9)
not	No change.
	The memory location pointed to by `address` is read.

Totally asynchronous memory operations occur when neither inclock nor outclock is connected. The output q is asynchronous and reflects the memory location pointed to by address.

Asynchronous Memory Operations

`WE`	Function Note (9)
L	No change (clock not enabled).
H	The memory location pointed to by `address` is loaded with `data` and controlled by `we`.

Resource Usage:

Uses one embedded cell per data output bit for ACEX 1K, APEX 20K, APEX II, ARM-based Excalibur, FLEX 10KE, and Mercury devices; however, in FLEX 6000, MAX 3000, and MAX 7000 devices, or if the USE_EAB parameter is set to "OFF", uses one logic cell per memory bit.

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