See Also

Inserting an HDL Template

Implementing Combinatorial Logic
      Using Continuous Assignments
      Using Always Constructs
Implementing Sequential Logic
      Implementing Registers
      Implementing Counters
      Implementing Latches
      Implementing State Machines
Creating Hierarchical Projects
      Using a Quartus^® II Logic Function
      Using a Verilog HDL Gate Primitive
      Implementing a User-Defined Megafunction or Macrofunction
      Using Parameterized Functions
      Implementing CAM, RAM & ROM
      Implementing Inferred RAM

For more information about using Verilog HDL in the Quartus II software, see Application Note 238 (Quartus II RTL Integrated Synthesis Design Methodology).

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