FPGA Timing Models

• Most FPGA and CPLD vendors provide a timing model in their data sheets that allow estimation of path delays.

• Some example path delays that are of interest:

  • Minimum Pin to Pin delay
    • (through input pin, through one combinational logic element, through one output pin.)
  • Minimum Register to Register Delay
    • .From clock input pin, through global net . through Clock to Q delay through DFF of a logic element, through one combinational logic element to setup time on DFF input).

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