FPGA Timing Models (cont)

• These timing models allow estimations of maximum attainable performance

• Some vendors use their timing models as selling points

  • Simpler is better - easier to estimate timing from a simple model than a complex one.
  • Routing delays will always complicate the timing model

• After a design is mapped to an FPGA or CPLD, always must use a static timing analysis program to compute the timing performance.

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