EE 4713/6713 Lab Material

This document contains links to the lab handouts used in EE4713/6713, Computer Architecture

• Running the Model Tech VHDL Simulator on your PC
• DLXSIM Manual Page
• DLXSIM Homework Assignment
• Sim 1: DLX Single Cycle Simulation
• Sim 2: DLX Single Cycle Memory Interface
• Sim 3: DLX Multi-Cycle Implementation
• Sim 4: DLX Multi-Cycle Implementation (Part 2)
• Sim 5: DLX Pipelined Implementation