DLX MultiCycle Implementation: Due Feb 25 at Class Time

Introduction

The goal of this simulation is to introduce the student to the concept of multicycle control for an ISA. You will be given a VHDL model of the multi-cycle implementation as discussed in the textbook. Your job will be to extend the multicycle implementation to handle BNEZ, immediate adds/subtracts (both signed and unsigned), and all of the byte/half-word loads/stores. Your program must be able to successfully execute both acid_test.s and mem_test.s programs we used to test the single cycle implementation.

Set Up

Copy the file '~reese/vhdl.tar.Z.sim3' from my ECE acccount to your local directory. Unpack this compressed tar file by doing:

   % cat vhdl.tar.Z.sim3 | zcat | tar xf -

This model runs 'as is'; it implements the multi-cycle control discussed in the book. You can test it by doing:

 qhsim -lib ../obj/qhdl/dlxmcyc cfg_mcyc_test

What You Have To Do

Your job will be to extend the multicycle implementation to handle BNEZ, immediate adds/subtracts (both signed and unsigned), and all of the byte/half-word loads/stores. Your program must be able to successfully execute both the acid_test.s (cfg_acid_test) and mem_test.s (cfg_mem_test) programs we used to test the single cycle implementation.

Tips

This task is more challenging than previous assignments. You will probably end up editing both 'dlx.vhd' and 'control.vhd' to get the job done. Before you write any VHDL code you should do the following:

• Understand the current code! You should read 'dlx.vhd', 'control.vhd' and understand what is going on; you should read the comments at the top of 'dlx.vhd' to see how this implementation differs from the textbook.
• Adding support for the other instructions involves adding new states; you should add them to the state diagram and understand what control lines need to be affected in each added state.

Adding States to 'control.vhd'

1. Pick a name for the state and a state encoding and add it as a CONSTANT declaration as the other states are done. You MUST pick a unique state encoding; if you don't then your code will NOT operate correctly.
2. Enter the code for the new state in the CASE statement which implements the logic for the control finite state machine. Remember, you have to modify an old state to check for some condition that makes it jump to your new state, and your new state must sequence to some other state (perhaps another new state, perhaps an existing state).

Adding a new port to a VHDL model

You may also find it necessary to add a new port (either input or output) to a VHDL model. For example, assume we adding a new output signal to the 'control.vhd' code. You should:

1. Add it to the port list of the entity declaration.
2. Add it to the process block. If it is an output, you should assign it some default value. If it is an input, you need to add it to the sensitivity list of the process block.
3. In 'dlx.vhd', add the signal to the component declaration for 'control.vhd'.
4. In 'dlx.vhd', add the signal to the 'port map' of the control block instance; you will need to connect it to some signal or port declared in 'dlx.vhd'. If it is an internal signal (not an external port), you will need to declare this internal signal.

To Turn In

You must turn in hardcopy of any files you have modified with your changes HIGHLIGHTED so I can easily see what you did. Print these files out in double column format to save paper. You must also do the following submission procedure:

1. Create a directory called 'sim3'.
2. Copy ONLY the vhdl files which you have modified to this directory.
3. Put a README file in the 'sim3' directory which tells me the status of your simulation (working or not working, if not working, then describe what is broken).
4. Execute the script '~reese/bin/submit_sim3.sh' from the directory ABOVE the 'sim3' directory (from the current directory, you should be able to see 'sim3' as a subdirectory). This will pack up the contents of the 'sim3' directory and email them to me.