Map Signals Explicitly (cont.)

Follow these steps to continue mapping connections between I/O signals in blocks to differently named I/O signals in other blocks:

  1. Repeat steps 1-7 described in Step 7: Map Signals Explicitly to map the connections listed in the following table:

    2. Connection: Type: I/O on Block: Signals in Bus:
    Bus from the taps block to the dataa[7..0] input of the mult symbol (already entered) OUTPUT x[7..0] dataa[7..0]
    Bus from the hvalues block to the datab[2..0] input of the mult symbol OUTPUT h[2..0] datab[2..0]
    Bus from the result[10..0] output of the mult symbol to the acc block INPUT xh[10..0] result[10..0]
    Bus from the acc block to the D input of the DFFE primitive BIDIR yn[7..0] yn[7..0]

    Show Me

    Completed filtref.bdf Block Design File

  2. Choose Save (File menu). The BDF is complete.


To continue the tutorial, proceed to Section 4: Create Verilog Design Files.