Now that you have created the blocks, you need to create the design files that the blocks represent. You can automatically create a design file that contains the basic framework for the block that represents it. You can then fill in the framework with the design details.
If you are already familiar with Verilog HDL design entry using the Quartus II Text Editor, you can reduce the time required to complete this tutorial by following the instructions in Copying Altera-Provided Design Files, rather than creating the files from scratch. |
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