ME95 Verilog WWW Pages
Student developed pages - Verilog Topics
Delay Modelling
Introduction
(Tomasz Wozniak)
Types of delay:
(Trude Iversen)
Delay triplets:
(David Allen)
Specify Block:
(Arthur MacDougall)
Path and conditional delays:
(Alastair Cook)
Timing checks
(Richard Humphreys)
Switch Level Modelling
Two examples:
(Chun Ng)
Syntax:
(David Eke)
Signal strengths:
(Stewart Penman)
Ambiguous signal strengths:
(Andrew Murdoch)
Tasks and Functions
Verilog tasks
(Ben Findlay)
Verilog functions
(Caroline Barker)
Miscellaneous
Hierarchical design
(David Low)
Parameterized modules
(Michael Scott)
Blocking vs. Non-blocking assignments
(Jeremy Hebblethwaite)
Serial vs. Parallel blocks
(David McCall)
Wait
(Catriona McKay)
Unsized vs. Sized numbers
(Nick Thomas)
x & z in if and case statements
(Craig Rankin)