Alternate VHDL specification

architecture a of compa is

begin

aeqb <= '1' when (a = b) else '0';

agtb <= '1' when (a > b) else '0';

altb <= '1' when (a < b) else '0';

end a;

Synthesis tool will pick a logic implementation for implementation of ‘=‘, ‘>’, ‘<‘ based on user constraints such as propagation delay.

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