PPT Slide

architecture a of comp is

signal en, skip: std_logic_vector(8 downto 0);

begin

aeqb <= en(0);

agtb <= skip(0);

altb <= (not en(0)) and (not skip(0));

process (a,b)

begin

en(8) <= '1'; skip(8) <= '0';

for i in 7 downto 0 loop

en(i) <= not (a(i) xor b(i)) and en(i+1);

if (skip(i+1) = '1') then

skip(i) <= '1';

else

skip(i) <= en(i+1) and (a(i) and not b(i));

end if;

end loop;

end process;

end a;

VHDL architecture that implements comparator logic as shown on previous slides.

Previous slide

Next slide

Back to first slide

View graphic version