MultiStage Gates
For multistage gates, determine the transistor sizes for the 1X gate that meets the DC switching point, delay ratio targets and that optimizes the NOLOAD delay (no output capacitance load).
When scaling the 1X size, the transistors which drive the final load are scaled by 1X, 2X, 3X, etc; internal stage transistors are scaled by less than this factor (anywhere from 0.0x to 0.5x usually).