Determining the 1X sized gate (cont)
To pullup, both PMOS needs to be on, so ‘L’s of the two transistor’s add. To pulldown, one NMOS must be on. These trees will have equivalent delays to a 1X inverter, but DC switching point will be closer to VDD.
Converting to equivalent 1X inverter W/L ratios produces conservative results. For the NOR, the pmos W’s will be able to be sized smaller than 2W of the 1X inverter. For the NAND, the nmos W’s will be able to be sized smaller than 2W of the 1X inverter.