This research started in June of 1995, and the present phase will continue into 1997. In the first phase of this research, we identified two major areas for improving simulation performance. The first area is development of VHDL component models and utilities that are commonly used in designs. In modeling of these utilities, we use our modeling expertise to develop configurable VHDL code for commonly used components and utility functions. The second area of our research focuses on development of modeling techniques for faster simulation. Generally these techniques apply to RT level descriptions and an automatic translator is being considered. The translator converts standart RTL VHDL code to one that simulates faster.