After you compile a design, you can view the timing analysis results in the Compilation Report. By default, the Timing Analyzer reports the maximum frequency (fMAX) of every register, the worst-case register-to-register delays, the input setup (tSU) and input hold (tH) times of every input register, the clock-to-output (tCO) delays of every output register, and the pin-to-pin (tPD) delays between all pins. In addition, you can customize the timing analysis by specifying timing requirements and other options.
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