Overview: Mapping Signals between Blocks (cont.)

The following table explains which signals in the filtref.bdf design are connected by the Quartus II software automatically through "smart" mapping. The following connections make use of "smart" block mapping—you do not need to explicitly name these connections:

From: To:
INPUT pin clk Block I/Os named clk in blocks that are connected to the clk pin
INPUT pins d[7..0]

Block I/Os that are named d[7..0] in the taps block
INPUT pin reset Block I/Os named reset in the taps and state_m blocks
INPUT pin newt Block I/Os named newt in the taps and state_m blocks
Block I/O named sel[1..0] in the taps block Block I/Os named sel[1..0] in the hvalues and state_m blocks
Block I/O named first in the state_m block Block I/Os named first in the acc block
Block I/O named next in the state_m block OUTPUT pin next


To continue the tutorial, proceed to Step 6: Map Signals by Name.