Step 1: Create a New Verilog Design File for the hvalues block

To create the framework of a Verilog Design File for the hvalues block, follow these steps:

1. Select the hvalues block.

2. Choose Create Design File from Selected Block (right button pop-up menu). The Create Design File from Selected Block dialog box appears.

3. Under File type, select Verilog HDL.

4. Make sure Add the new design file to the current project is turned on.

5. Make sure the File name box shows the hvalues.v file in the fir_filter project directory.

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6. Click OK. The Quartus II software confirms that the file has been generated successfully and automatically opens a Text Editor window that contains the new file. The Quartus II software generates the file shown below, which includes a template for a module declaration containing port declarations that correspond to the data you entered in the block:

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You may notice a few pairs of Quartus II-generated comments that start with "ALTERA" and end with "DO NOT REMOVE THIS LINE!" The Quartus II software updates the information between these pairs of comments, so you must not enter text between them. However, you can enter other Verilog HDL statements outside these commented sections.

7. Add the following lines to the hvalues.v file to implement the design. Insert these lines just before the endmodule statement:

   reg [2:0]h;
   
   always @(sel)
   case (sel)
          	2'b 00 : h = 3'b 111;
          	2'b 01 : h = 3'b 101;
          	2'b 10 : h = 3'b 011;
          	2'b 11 : h = 3'b 001;
   endcase
   

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8. Choose Save (File menu).

9. To close the Text Editor, choose Close (File menu).