Step 2: Copy Verilog Design Files for Other Blocks

You can copy the Verilog Design Files that are provided for the taps, state_m, and acc blocks. To copy the taps.v, state_m.v, and acc.v files from the \qdesigns\tutorial subdirectory into the \qdesigns\fir_filter subdirectory, follow these steps for each file:

1. Choose Open (File menu). The Open dialog box appears.

2. In the Files of type list, select Device Design Files.

3. In the \qdesigns\tutorial subdirectory, select the taps.v, state_m.v, or acc.v Altera-provided file in the Files list.

4. Click Open.

5. Choose Save As (File menu). The Save As dialog box appears.

6. In the Save in list, select \qdesigns\fir_filter as the target directory.

7. Make sure Add file to current project is turned on.

8. Click Save.

9. Repeat these steps for each file.