The Quartus II software offers three views of a design's floorplan:
The Current Assignments floorplan allows you to edit the location assignments of resources on the device.
The non-editable Last Compilation floorplan shows how the Compiler implemented the design in a device.
The Timing Closure floorplan unifies the Last Compilation and Current Assignments floorplans, which helps you to create effective LogicLock™ regions to enable faster design timing closure.
The Current Assignments and Last Compilation floorplans allow you to view information organized by interior logic cells, interior LABs, interior MegaLAB structures, and the device package top and bottom. The Timing Closure Floorplan is described in greater detail in the LogicLock tutorial module.
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