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| Name: | Function: | Default Logic Level: | ||
CLK |
= | register clock input | none | |
CLRN |
= | clear input | VCC (inactive) | |
D, J, K, R, S, T |
= | data input from logic array | none | |
ENA |
= | latch enable or clock enable input | VCC (active) | |
PRN |
= | preset input | VCC (inactive) | |
ADATA |
= | asynchronous data input | none | |
ALOAD |
= | asynchronous load input | GND (inactive) | |
Q |
= | output | n/a |
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- PLDWorld - |
- Last Modified: 01/05/2003 12:03:26 - |
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