TFF Primitive
 
AHDL Function Prototype (port name and order also apply to Verilog HDL):
FUNCTION TFF (T, CLK, CLRN, PRN)
   RETURNS (Q);
VHDL Component Declaration:
COMPONENT TFF
   PORT (t   : IN STD_LOGIC;
      clk : IN STD_LOGIC;
      clrn: IN STD_LOGIC;
      prn : IN STD_LOGIC;
      q   : OUT STD_LOGIC);
END COMPONENT;
 
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     H | 
     X | 
     X | 
     
	 
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     L | 
     X | 
     X | 
     
	 
	  | L | 
     L | 
     X | 
     X | 
	  
	 
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     H | 
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     L | 
	  
	 
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     H | 
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     H | 
	  
	 
	  | H | 
     H | 
     L | 
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     | Qo* | 
     
	 
	  | Toggle | 
	  
	 
     | Qo* | 
     
	 
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*	Qo = level of Q before clock pulse
All flipflops are positive-edge-triggered. 
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