Megafunction

lpm_dff (D Flipflop & Shift Register) Megafunction

Parameterized D-type flipflop and shift register megafunction. Altera® recommends that you use lpm_ff rather than lpm_dff for flipflop functions, and lpm_shiftreg for shift register functions. The lpm_dff megafunction is provided only for backward compatibility.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_dff (data[LPM_WIDTH-1..0], clock, enable, shiftin, shiften,
      sclr, sset, sconst, aclr, aset, aconst)
   WITH (LPM_WIDTH, LPM_AVALUE, LPM_SVALUE)
   RETURNS (q[LPM_WIDTH-1..0], shiftout);

NOTE The sconst and aconst ports are provided only for backward compatibility, but should be left unconnected in newer projects.

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
data[] No Data input to the flipflops. Input port LPM_WIDTH wide. If the data[] input is not used, at least one of the aset, aclr, sset, sclr and/or the combination of shiftin and shiften must be used.
clock Yes Positive-edge-triggered clock.
enable No Clock enable input. Default = 1.
shiftin No Serial shift data input. The shift options also use the enable input for the clock enable. For serial operation, both shiften and enable must be high.
shiften No Shift enable input. High (1) = shift operation, low (0) = register operation. Default = 0 (register operation).
sclr No Synchronous clear input. If both sset and sclr are used and both are asserted, sclr is dominant. The sclr signal affects the q[] outputs before polarity is applied to the ports.
sset No Synchronous set input. Sets q[] outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1s. If both sset and sclr are used and both are asserted, sclr is dominant. The sset affects the q[] outputs before polarity is applied to the ports.
aclr No Asynchronous clear input. If both aset and aclr are used and both are asserted, aclr is dominant. The aclr signal affects the q[] outputs before polarity is applied to the ports.
aset No Asynchronous set input. Sets q[] outputs to the value specified by LPM_AVALUE, if that value is present, or sets the q[] outputs to all 1s. If both aset and aclr are used and both are asserted, aclr is dominant. The aset signal affects the q[] outputs before polarity is applied to the ports.

OUTPUT PORTS

Port Name Required Description Comments
q[] No Data output from flipflops. Output port LPM_WIDTH wide. Either q[] or shiftout or both must be used.
shiftout No Serial shift data output. Output port. Either q[] or shiftout or both must be used.

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of the data[] and q[] ports.
LPM_AVALUE Integer / String No Constant value that is loaded when aset is high. If omitted, defaults to all 1s. The LPM_AVALUE parameter is limited to a maximum of 32 bits. Altera recommends that you specify this value as a decimal number for AHDL designs.
LPM_SVALUE Integer / String No Constant value that is loaded on the rising edge of clock when sset is high. If omitted, defaults to all 1s. Altera recommends that you specify this value as a decimal number for AHDL designs.

 

Truth Table/Functionality:
Inputs Outputs
aclr aset enable clock sclr sset sload q[LPM_WIDTH-1..0]
1 x x x x x x 000...
0 1 x x x x x 111... or LPM_AVALUE
0 0 0 x x x x q[LPM_WIDTH-1..0]
0 0 1 Rising Edge 1 x x 000...
0 0 1 Rising Edge 0 1 x 111... or LPM_SVALUE
0 0 1 Rising Edge 0 0 1 q[LPM_WIDTH-1..0], shiftin
0 0 1 Rising Edge 0 0 0 data[LPM_WIDTH-1..0]

 

Resource Usage:

Uses one logic cell per bit.

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