Megafunction

lpm_shiftreg (Universal Shift Register) Megafunction

Parameterized shift register megafunction. Altera® recommends that you use the lpm_shiftreg function to replace all other types of shift register functions.

Altera also recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_shiftreg (data[LPM_WIDTH-1..0], clock, enable, shiftin, load, sclr, sset, aclr, aset)
   WITH (LPM_WIDTH, LPM_DIRECTION, LPM_AVALUE, LPM_SVALUE)
   RETURNS (q[LPM_WIDTH-1..0], shiftout);

 

VHDL Component Declaration:

 
COMPONENT lpm_shiftreg
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_AVALUE: STRING := "UNUSED";
      LPM_SVALUE: STRING := "UNUSED";	  
      LPM_PVALUE: STRING := "UNUSED";
      LPM_DIRECTION: STRING := "UNUSED";
      LPM_TYPE: STRING := "LPM_SHIFTREG";
      LPM_HINT: STRING := "UNUSED");
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
      clock: IN STD_LOGIC;
      enable, shiftin: IN STD_LOGIC := '1';
      load, sclr, sset, aclr, aset: IN STD_LOGIC := '0';
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      shiftout: OUT STD_LOGIC);
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
data[] No Data input to the shift register. Input port LPM_WIDTH wide. At least one of the data, aset, aclr, sset, sclr and/or shiftin ports must be used.
clock Yes Positive-edge-triggered clock.  
enable No Clock enable input. The shift options also use the enable input for the clock enable. For serial operation, enable must be high (1). For parallel load operation, load must be high (1) and enable must be high or unconnected.
shiftin No Serial shift data input. At least one of the data, aset, aclr, sset, sclr and/or shiftin ports must be used. The default value is VCC.
load No Synchronous parallel load. High (1): load operation; low (0): shift operation. Default is low (0) shift operation. For parallel load operation, load must be high (1) and enable must be high or unconnected.
sclr No Synchronous clear input. If both sset and sclr are used and both are asserted, sclr is dominant. The sclr signal affects the q[] outputs before polarity is applied to the ports.
sset No Synchronous set input. Sets q outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1s. If both sset and sclr are used and both are asserted, sclr is dominant. The sset signal affects the q[] outputs before polarity is applied to the ports.
aclr No Asynchronous clear input. If both aset and aclr are used and both are asserted, aclr is dominant. The aclr signal affects the q[] outputs before polarity is applied to the ports.
aset No Asynchronous set input. Sets q[] outputs to the value specified by LPM_AVALUE, if that value is present, or sets the q[] outputs to all 1s. If both aset and aclr are used and both are asserted, aclr is dominant. The aset signal affects the q[] outputs before polarity is applied to the ports.

OUTPUT PORTS

Port Name Required Description Comments
q[] No Data output from the shift register. Output port LPM_WIDTH wide. Either q[] or shiftout or both must be used.
shiftout No Serial shift data output. Either q[] or shiftout or both must be used. The shiftout port value is equal to q[LPM_WIDTH-1] when LPM_DIRECTION="LEFT". When LPM_DIRECTION="RIGHT", shiftout equals q[0].

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of the data[] and q ports.
LPM_DIRECTION String No Values are "LEFT", "RIGHT", and "UNUSED". If omitted, the default is "LEFT". The MSB is the leftmost bit and the LSB is the rightmost bit. The MSB is q[LPM_WIDTH-1].
LPM_AVALUE Integer / String No Constant value that is loaded when aset is high. If omitted, defaults to all 1s. The LPM_AVALUE parameter is limited to a maximum of 32 bits. Altera recommends that you specify this value as a decimal number for AHDL designs.
LPM_SVALUE Integer / String No Constant value that is loaded on the rising edge of clock when sset is high. If omitted, defaults to all 1s. Altera recommends that you specify this value as a decimal number for AHDL designs.
LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.

 

Truth Table/Functionality:
Inputs Outputs
aclr aset enable clock sclr sset sload Q[LPM_WIDTH-1..0]
1 x x x x x x 000...
0 1 x x x x x 111... or LPM_AVALUE
0 0 0 x x x x q[LPM_WIDTH-1..0]
0 0 1 Rising Edge 1 x x 000...
0 0 1 Rising Edge 0 1 x 111... or LPM_SVALUE
0 0 1 Rising Edge 0 0 1 data[LPM_WIDTH-1..0]
0 0 1 Rising Edge 0 0 0 q[LPM_WIDTH-2..0], shiftin
(assuming LPM_DIRECTION = "LEFT")

 

Resource Usage:

Uses one logic cell per bit.

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