Select your Programmable Logic Device for building your SoC (System On Chip)...

 

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Device Family Largest Device Capacity, Basic Cells Capacity, Eq Gates MAX User IO Pin Number Technology Process
Xilinx 4000 XC40250XV 8,464 CLBs 250,000 448 SRAM 0.25 µm
Xilinx Virtex, Virtex-E XCV3200E 73,008 LCs 4,074,387 804 SRAM 0.18 µm
Altera FLEX 8000 81500 1,296 LEs 16,000 208 SRAM 0.5 µm
Altera FLEX 10K EPF10K250 12,160 LEs 250,000 470 SRAM 0.25 µm
Altera Apex20K, Apex20KE EP20K1500E 51,840 LEs 1,500,000 808 SRAM 0.18 µm
Actel PROASIC A500K510 51,200 tiles 410,000 623 Flash 0.25 µm
Lucent ORCA OR3L225B 11,552 LUTs 340,000 612 SRAM 0.25 µm

 

Device Family Logic Primitive Basic Cell (CLB) Architecture
Xilinx 4000 LUT4 2 4-Input LUTs, 1 3-Input LUT, 2 FF per CLB (F, G, H-Function Generators) CLBs organized in rows and columns
Xilinx Virtex, Virtex-E LUT4 2 LUTs per SLICE, 2 SLICES per CLB, 4 FF per CLB CLB organized in rows and columns
Altera FLEX 8000 LUT4 1 LUT, 1 FF per Logic Element (LE) 8 LEs per LAB, LABs organized in rows and columns
Altera FLEX 10K LUT4 1 LUT, 1 FF per Logic Element (LE) 8 LEs per LAB, LABs organized in rows and columns
Altera
Apex20K,
Apex20KE		 LUT4 1 LUT, 1 FF per Logic Element (LE) MultiCore : LUT, Product Term, Memory; 10 Les per LAB, 16 LABs per MegaLAB, MegaLABs organized in rows and columns
Actel PROASIC 3 input - 1 output tile Tile can be configured either as a comb. Cell or as FF Tiles are organized in blocks, blocks of tiles are organized in rows and columns
Lucent ORCA LUT4 PLC consists of a PFU and a SLIC; PFU contains 8 LUT4 and 9 FFs Arrays of PLCs, the whole array is split in four quadrants

 

Device Family Interconnect Carry Chains Memories Clock Management
Xilinx 4000 CLB routing : vertical and horizontal channels (single-length, double-length, quad, octal lines and long lines), Programmable Switch Matrices YES 270K RAM bits of Distributed Select RAM N/A
Xilinx Virtex, Virtex-E FastConnect - intra-CLB, local routing, general purpose routing (horizontal and vertical channels) YES 851K RAM bits of BlockRAM + 1M of Distributed select RAM DLL
Altera FLEX 8000 Local Interconnect within LAB, row&Column Interconnect YES N/A N/A
Altera FLEX 10K Local Interconnect within LAB, Row & Column Interconnect YES 41K RAM bits of Embedded Array Blocks (EABs) PLL
Altera Apex20K, Apex20KE Local Interconnect within LAB, MegaLAB Interconnect, Row & Column Interconnect YES ESB capable to implement RAM, ROM, CAM, ProductTerm, 442K RAM PLL
Actel PROASIC Local network, long line network, bus network, global network NO MAX of 60 Embedded RAM Blocks (256 x 9) N/A
Lucent ORCA Segmented hierachical routing : Interquad routing, inter PLC routing YES 185K : implemented as a special operating mode of the PLCs PCM

 

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