Xilinx Development System Files...


 

Xilinx Development System Files

¾Æ·¡ÀÇ µµÇ¥´Â Xilinx Development Software°¡ »ç¿ëÇÏ´Â °¢Á¾ ÆÄÀϵéÀ» °£·«ÇÑ ¼³¸í°ú ÇÔ²² Á¤¸®ÇÑ °ÍÀÔ´Ï´Ù...  Software Çѹø µ¹¸®°í ³ª¸é, ¹¹°¡ ¹ºÁöµµ ¸ð¸¦ ¾Ë½ö´Þ½öÇÑ ¿©·¯°¡Áö È®ÀåÀÚ¸¦ °®´Â ÆÄÀϵéÀÌ ºÎÁö±â¼ö·Î »ý±âÁÒ...  ±×·²¶§ ÀÌ ¹®¼­¸¦ ÂüÁ¶ÇÏ½Ã¸é ¾à°£À̳ª¸¶ µµ¿òÀÌ µÇ½Ã¸®¶ó »ý°¢ÇÕ´Ï´Ù...

ÆÄÀϸí/È®ÀåÀÚ
ÆÄÀÏÇü½Ä
ÆÄÀÏ»ý¼º ÁÖü
°£´ÜÇÑ ¼³¸í
ALF
ASCII
NGDAnno
Log file containing information about an NGDAnno run
BIT
Data
BitGen
Download bitstream file for devices containing all of the configuration information from the NCD file
BGN
ASCII
BitGen
Report file containing information about a BitGen run
BLD
ASCII
NGDBuild
Report file containing information about an NGDBuild run, including the subprocesses run by NGDBuild
DATA
C File
TRCE
File created with the -stamp option to TRCE that contains timing model information
DC
ASCII
Synopsys FPGA Compiler
Synopsys setup file containing constraints read into the Xilinx Development System
DLY
ASCII
PAR
File containing delay information for each net in a design
DRC
ASCII
BitGen
Design Rule Check file produced by BitGen
EDIF (various file extensions)
ASCII
CAE vendor's EDIF 2 0 0 netlist writer.
EDIF netlist. The Xilinx Development System accepts an EDIF 2 0 0 Level 0 netlist file
EDN
ASCII
NGD2EDIF
Default extension for an EDIF 2 0 0 netlist file
EPL
ASCII
FPGA Editor
FPGA Editor command log file. The EPL file keeps a record of all FPGA Editor commands executed and output generated. It is used to recover an aborted FPGA Editor session
EXO
Data
PROMGen
PROM file in Motorola's EXORMAT format
FLW
ASCII
Provided with software
File containing command sequences for XFLOW programs
fpga_editor.ini
ASCII
Xilinx software
Script that determines what FPGA Editor commands are performed when the FPGA Editor starts up
fpga_editor_
user.ini
ASCII
Xilinx software
Supplement to the fpga_editor.ini file used for modifying or adding to the fpga_editor.ini file
GYD
ASCII
CPLD fitter
CPLD guide file
HEX
Hex
PROMGen Command
Output file from PROMGEN that contains a hexadecimal representation of a bitstream
IBS
ASCII
IBISWriter Command
Output file from IBISWriter that consists of a list of pins used by the design, the signals internal to the device that connect to those pins, and the IBIS buffer models for the IOBs connected to the pins
ITR
ASCII
PAR
Intermediate failing timespec summary from routing
JED
JEDEC
CPLD fitter
Programming file to be downloaded to a device
LOG
ASCII
NGD2VER

NGD2VHDL

XFLOW
Log file containing all the messages generated during the execution of NGD2VER (ngd2ver.log), NGD2VHDL (ngd2vhdl.log), or XFLOW (xflow.log)
LL
ASCII
BitGen
Optional ASCII logic allocation file with an .ll extension. The logic allocation file indicates the bitstream position of latches, flip-flops, and IOB inputs and outputs.
MEM
ASCII
User (with text editor)

LogiBLOX
User-edited memory file that defines the contents of a ROM
MCS
Data
PROMGen
PROM-formatted file in Intel's MCS-86 format
MDF
ASCII
MAP
A file describing how logic was decomposed when the design was mapped. The MDF file is used for guided mapping.
MFP
ASCII
Floorplanner
Map Floorplanner File, which is generated by the Floorplanner, specified as an input file with the -fp option. The MFP file is essentially used as a guide file for mapping.
MOD
ASCII
TRCE
File created with the -stamp option in TRCE that contains timing model information
MRP
ASCII
MAP
MAP report file containing information about a technology mapper command run
MSK
Data
BitGen
File used to compare relevant bit locations when reading back configuration data contained in an operating Xilinx device
NAV
XML
NGDBuild
Report file containing information about an NGDBuild run, including the subprocesses run by NGDBuild. From this file, the user can click any linked net or instance names to navigate back to the net or instance in the source design.
NCD
Data
Mappers, PAR, FPGA Editor
Flat physical design database correlated to the physical side of the NGD in order to provide coupling back to the user's original design
NCF
ASCII
CAE Vendor toolset
Vendor-specified logical constraints files
NGA
Data
NGDAnno
Back-annotated mapped NCD file
NGC
Binary
LogiBLOX
File containing the implementation of a module in the design
XST
Netlist file with constraint information
NGD
Data
NGDBuild
Generic Database file. This file contains a logical description of the design expressed both in terms of the hierarchy used when the design was first created and in terms of lower-level Xilinx primitives to which the hierarchy resolves.
NGM
Data
MAP
File containing all of the data in the input NGD file as well as information on the physical design produced by the mapping. The NGM file is used for back-annotation.
NGO
Data
Netlist Readers
File containing a logical description of the design in terms of its original components and hierarchy
NKY
Data
BitGen
Encryption key file
NMC
Binary
FPGA Editor
Xilinx physical macro library file containing a physical macro definition that can be instantiated into a design
OPT
Text
Input file option
Option file used by XFLOW
PAD
ASCII
PAR
File containing a listing of all I/O components used in the design and their associated primary pins
PAR
ASCII
PAR
PAR report file containing execution information about the PAR command run. The file shows the steps taken as the program converges on a placement and routing solution
partlist.xct
ASCII
PARTGen
File containing detailed information about architectures and devices
PCF
ASCII
MAP, FPGA Editor
File containing physical constraints specified during design entry (that is, schematics) and constraints added by the user
PIN
ASCII
NGD2VER
Cadence signal-to-pin mapping file
PRM
ASCII
PROMGen
File containing a memory map of a PROM file showing the starting and ending PROM address for each BIT file loaded
RBT
ASCII
BitGen
"Rawbits" file consisting of ASCII ones and zeros representing the data in the bitstream file
RPT
ASCII
PIN2UCF
Report file generated by PIN2UCF when conflicting constraints are discovered. The name is pinlock.rpt.
RCV
ASCII
FPGA Editor
FPGA Editor recovery file
SCR
ASCII
FPGA Editor or XFLOW
FPGA Editor or XFLOW command script file
SDF
ASCII
NGD2VER, NGD2VHDL
File containing the timing data for a design. Standard Delay Format File
TDR
ASCII
DRC
Physical DRC report file
TEK
Data
PROMGen
PROM-formatted file in Tektronix's TEKHEX format
TV
ASCII
NGD2VER
Verilog test fixture file
TVHD
ASCII
NGD2VHDL
VHDL testbench file
TWR
ASCII
TRACE
Timing report file produced by TRACE
TWX
XML
TRACE
Timing report file produced by TRACE. From this file, the user can click any linked net or instance names to navigate back to the net or instance in the source design.
UCF
ASCII
User (with text editor)
User-specified logical constraints files
URF
ASCII
User (with text editor)
User-specified rules file containing information about the acceptable netlist input files, netlist readers, and netlist reader options
V
ASCII
NGD2VER
Verilog netlist
VHD
ASCII
NGD2VHDL
VHDL netlist
VM6
Design
CPLD Fitter
Output file from fitter
XMM
ASCII
NGD2EDIF
File defining the initial contents of the RAMs in the design for a simulator
XNF
ASCII
Previous releases of Xilinx Development System, CAE vendor toolsets
Xilinx netlist format file
XTF
ASCII
Previous releases of Xilinx Development System
Xilinx netlist format file
XPI
ASCII
PAR
File containing PAR run summary

  Send to a colleague | Print this document