SDSP Bus Read Timing
-- Notes Page --
During a Ti state, the CPU places an address on
A_BUS
. T1 is the next state
After the leading edge of
phi1
, the CPU asserts
read
to initiate a read activity in the memory
If an instruction is being fetched,
fetch
is asserted
T2 states occur until
ready
is asserted by the memory
The CPU inputs data on rising edge of
phi1
and deasserts
read
(and
fetch
).
Memory deasserts
ready
on falling edge of
read
