VHDL Objects

   ARCHITECTURE variables OF test IS
       SIGNAL a: BIT:='0';
              b, c: BIT:='1';
   BEGIN
       PROCESS (a, b, c)
       VARIABLE out_3, out_4 : BIT;
       BEGIN
       out_3 := a NAND b;
       out_4 := out_3 XOR c;
       END PROCESS;
   END variables;