이곳은 인터넷상의 이곳 저곳에서 모은 각종 논문, 잡지 기고문, Conference 발표문서, 관련 Presentation 자료, 기술보고서등만을 따로 분류관리하는 페이지 입니다...

1. Cliff Cummings

• 출처: http://www.sunburst-design.com/papers/

2. Stuart Sutherland

• 출처: http://www.sutherland-hdl.com/papers.html
• online Verilog-1995 Quick Reference Guide (2016.6.21)

3. Don Mills

• 출처: http://www.lcdm-eng.com/papers.htm

• SNUG 02: Synchronous Resets? Asynchronous Resets? I Am So Confused! How Will I Ever Know Which to Use?
• SNUG 01: Getting the Most Out of the New Verilog-2000 Standard
• SNUG 00: Habits of Deficient ASIC Design
• SNUG 99: RTL Coding Styles That Yield Simulation and Synthesis Mismatches
• SNUG 97: Synthesis of a Million-Gate ASIC

4. Roman Lysecky

• 출처: http://www.cs.ucr.edu/~rlysecky/publications.html

Journal

• R. Lysecky, S. Cotterell, F. Vahid A Fast On-Chip Profiler Memory using a Pipelined Binary Tree. IEEE Transaction on Very Large Scale Integration (TVLSI), To Appear. PDF
• F. Vahid, R. Lysecky, C. Zhang, G. Stitt. Highly Configurable Platforms for Embedded Computing Systems. Invited Paper Microelectronics Journal, Elsevier Publishers, To Appear PDF
• R. Lysecky, F. Vahid. Pre-fetching for Improved Bus Wrapper Performance in Cores. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 7, Number 1, January 2002. PDF

Conference

• R. Lysecky, F. Vahid. A Codesigned On-Chip Logic Minimizer. CODES+ISSS 2003, To Appear, October 2003. PDF
• R. Lysecky, F. Vahid. On-Chip Logic Minimization. Design Automation Conference (DAC), June 2003. PDF   Slides
• G. Stitt, R. Lysecky, F. Vahid. Dynamic Hardware/Software Partitioning: A First Approach. Design Automation Conference (DAC), June 2003. PDF   Slides
• R. Lysecky, S. Cotterell, F. Vahid. A Fast On-Chip Profiler Memory. Design Automation Conference (DAC), pp. 28-33, June 2002. PDF   Slides
• G. Stitt, F. Vahid, T. Givargis, R. Lysecky. A First-step Towards an Architecture Tuning Methodology for Low Power. Compilers, Architectures, and Synthesis for Embedded Systems (CASES), pp. 187-192, Novemeber 2000. PDF   Slides
• R. Lysecky, F. Vahid, T. Givargis. Experiments with the Peripheral Virtual Component Interface. International Symposium on System Synthesis (ISSS), pp. 221-224, September 2000. PDF   Slides
• R. Lysecky, F. Vahid, T. Givargis. Techniques for Reducing Read Latency of Core Bus Wrappers. Design Automation and Test in Europe (DATE) Conference, pp. 84-91, March 2000. PDF   Slides
  Received Best Paper Award
• R. Lysecky, F. Vahid, T. Givargis, R. Patel. Pre-fetching for Improved Core Interfacing. International Symposium on System Synthesis (ISSS), pp. 51-55, November 1999. PDF   Slides

5. Krishna Sekar (2004.3.1)

• 출처: http://aspire.ucsd.edu/~ksekar/publications.html

Journal Articles:

• K.Sekar, S.Dey, "LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects", in Journal of Electronic Testing: Theory and Applications, Vol. 19, No. 2, pp.113-123, April 2003. pdf

Conference Publications:

• K.Sekar, K.Lahiri, S.Dey, "Dynamic Platform Management for Configurable Platform-Based System-on-Chips", to appear in Proc. International Conference on Computer-Aided Design, San Jose, Nov 2003. pdf
• K.Sekar, S.Dey, "LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects", in Proc. 20th IEEE VLSI Test Symposium, Monterey, May 2002. pdf
• I.Ghosh, K.Sekar, V.Boppana, "Design for Verification at the Register Transfer Level", in International Conference on VLSI Design and Asia and South Pacific Design Automation Conference, pp.420-425, Bangalore, January 2002. pdf
• P.Dasgupta, P.P.Chakrabarti, A.Nandi, K.Sekar, A.Chakrabarti, "Abstraction of Word-level Linear Arithmetic Functions from Bit-level Component Descriptions", in Design, Automation, and Test in Europe, pp.4-8, Munich, March 2001. pdf
• S.Dey, P.Sanchez, D.Panigrahi, L.Chen, C.Taylor, K.Sekar, "Using a Soft Core in a SOC Design: Experiences with picoJava", IEEE Design and Test of Computers, vol.17, no.3, pp.60-71, July-September 2000. pdf
• L.Chen, S.Dey, P.Sanchez, K.Sekar, Y.H.Chen, "Embedded Hardware and Software Self-Testing Methodologies for Processor Cores", in Proc. 37th Design Automation Conference, Los Angeles, June 2000. pdf

6. DiVA portal - Linköping University

DiVA portal is a finding tool for research publications and student theses written at the several universities and research institutions.

• 출처: http://liu.diva-portal.org/smash/resultList.jsf?query=fpga&language=en&searchType=SIMPLE&noOfRows=250&sortOrder=title_sort_asc&onlyFullText=true&sf=all&aq=[[]]&aqe=[]&aq2=[[]]
• 출처: http://liu.diva-portal.org/smash/resultList.jsf?query=vhdl&language=en&searchType=SIMPLE&noOfRows=250&sortOrder=title_sort_asc&onlyFullText=true&sf=all&aq=[[]]&aqe=[]&aq2=[[]]
• 출처: http://liu.diva-portal.org/smash/resultList.jsf?query=verilog&language=en&searchType=SIMPLE&noOfRows=250&sortOrder=title_sort_asc&onlyFullText=true&sf=all&aq=[[]]&aqe=[]&aq2=[[]]

Other Papers...

• Rindert Schutten, Tom Fitzpatrick, Design for Verification - Blueprint for Productivity and Product Quality, Synopsys, Inc. April 2003
• Lavi Lev, Ted Vucurevich, Right on time -- requirements for advanced custom design, EEdesign, August 22, 2003 (5:28 p.m. EST)
• Graham Prophet, Editor, EDN Europe, Structured ASICs: More gain, less pain?, EDN Europe, 8/7/2003
• Ron Wilson, 'Structured' ASICs arrive, EE Times, May 5, 2003 (10:23 a.m. EST)
• Kapil Batra, Mohammad Suhaib Husain, Verilog Coding Style For Efficient Digital Design

• Keyvani, Maryam. 2001. VHDL Implementation of a High-Speed Symmetric Crossbar Switch, M.A.Sc., Engineering Science, Simon Fraser University. (2004.5.15)
• Stephen D. Scott, Sharad Seth, and Ashok Samal. A synthesizable VHDL coding of a genetic algorithm. Technical report UNL-CSE-97-009, University of Nebraska-Lincoln, November 1997. Includes detailed description of functionality of the HGA's VHDL code. (2004.8.15)
• Young Kyu Kang, Dae Won Kim, Taek Won Kwon, Jun Rim Choi, Hash Function Processor Using Resource Sharing for IPSEC Chip , Kyungpook National University, School of Electronic Engineering (2004.12.03)
• 강용규, 석정희, 최준림, PCI Bus 기반의 IPSEC용 Hash 함수의 FPGA 설계 , 경북대학교 전자공학과 (2004.12.03)
• Douglas J. Smith, VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C , DAC'96 (2006.5.7)