library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity tb_simple2 is
end tb_simple2;


architecture structure of tb_simple2 is


component sram2
   generic(
           mem_words: integer := 32
        );
   port(
        RST:    in  std_logic; -- doesn't go to RAM, but is useful for testing
        A:      in  std_logic_vector(7 downto 0);
        WE_L:   in  std_logic;
        RD_L:   in  std_logic;
        
        D:      inout  std_logic_vector(7 downto 0)
       );
end component;



component mp
   port(
        RST:    in     std_logic;
        A:      out    std_logic_vector(7 downto 0);
        WE_L:   out    std_logic;
        RD_L:   out    std_logic;
        D:      inout  std_logic_vector(7 downto 0)
       );
end component;



signal D:     std_logic_vector(7 downto 0);
signal A:     std_logic_vector(7 downto 0);
signal WE_L:  std_logic;
signal RD_L:  std_logic;
signal RST:   std_logic;



begin
   
RST <= '0', '1' after 1 ns, '0' after 2 ns;   


U_SIMPLE_SRAM: SRAM2
   port map (
    RST  => rst,
    A    => a,
    WE_L => we_l,
    RD_L => rd_l,
    D    => d
   );



U_MP: MP
   port map (
    RST  => rst,
    A    => a,
    WE_L => we_l,
    RD_L => rd_l,
    D    => d
   );


end structure;