library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity tb_simple is
end tb_simple;


architecture structure of tb_simple is


component simple_sram
   port(
        A:      in  std_logic_vector(7 downto 0);
        WE_L:   in  std_logic;
        
        D:      inout  std_logic_vector(7 downto 0)
       );
end component;


component stim_gen
   port(
        A:      out  std_logic_vector(7 downto 0);
        WE_L:   out  std_logic;
        D:      out  std_logic_vector(7 downto 0)
       );
end component;


signal D:  std_logic_vector(7 downto 0);
signal A:  std_logic_vector(7 downto 0);
signal WE_L:  std_logic;

begin

U_SIMPLE_SRAM: SIMPLE_SRAM
   port map (
    A    => a,
    WE_L => we_l,
    D    => d
   );

U_STIM_GEN: STIM_GEN
   port map (
    A    => a,
    WE_L => we_l,
    D    => d
   );

end structure;