library ieee;
use ieee.std_logic_1164.all;
 
 
entity TB_CLK_RST is
end TB_CLK_RST; 


architecture test of TB_CLK_RST is

signal clk: std_logic := '0';
signal rst: std_logic;

begin

rst <= '0', '1' after 10 ns, '0' after 30 ns;
clk <= not clk after 8 ns;
 
end test;