library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

use work.txt_util.all;
 
 
entity STIM_GEN is
   port(
        A:      out  std_logic_vector(7 downto 0);
        WE_L:   out  std_logic;
        D:      out  std_logic_vector(7 downto 0)
       );
end STIM_GEN; 


architecture test of STIM_GEN is


constant tSU       : time :=  4 ns;
constant tH        : time :=  3 ns;
constant tW_WE     : time := 40 ns;

signal clk: std_logic := '0';
signal rst: std_logic;

begin

rst <= '0', '1' after 10 ns, '0' after 30 ns;
clk <= not clk after 8 ns;



test_seq: process
begin
  
A    <= (others => 'X');
D    <= (others => 'Z');
WE_L <= '1';

wait for 20 ns;

-----------------------------

print(" ");
print(" one correct access");

A    <= "00000000";
D    <= "11110000";

wait for 4 ns;

WE_L <= '0';

wait for 40 ns;

WE_L <= '1';

wait for 3 ns;

A    <= (others => 'X');
D    <= (others => 'Z');

wait for 10 ns;
                                    
-----------------------------

print(" ");
print(" wrong address and wrong data");

A    <= "00000000";
D    <= "11110000";

wait for 4 ns;

WE_L <= '0';

wait for 40 ns;

WE_L <= '1';

wait for 3 ns;

A    <= (others => 'X');
D    <= (others => 'Z');

wait for 10 ns;

-----------------------------

print(" ");
print(" violate address setup and data hold time");

D    <= "11110000";

wait for 1 ns;

A    <= "00000000";

wait for 3 ns;

WE_L <= '0';

wait for 40 ns;

WE_L <= '1';

wait for 2 ns;

D    <= (others => 'Z');

wait for 1 ns;

A    <= (others => 'X');

wait for 10 ns;
                                    

-----------------------------

print(" ");
print(" violate data setup and address hold time");

A    <= "00000001";

wait for 1 ns;

D    <= "00001111";

wait for 3 ns;

WE_L <= '0';

wait for 40 ns;

WE_L <= '1';

wait for 2 ns;

A    <= (others => 'X');

wait for 1 ns;

D    <= (others => 'Z');

wait for 10 ns;

-----------------------------

print(" ");
print(" pulse width too short");

A    <= "00000000";
D    <= "11110000";

wait for 4 ns;

WE_L <= '0';

wait for 30 ns;

WE_L <= '1';

wait for 3 ns;

A    <= (others => 'X');
D    <= (others => 'Z');

wait for 10 ns;
                                    

-----------------------------

print(" ");
print(" unstable address");

A    <= "00000001";
D    <= "00001111";

wait for 4 ns;

WE_L <= '0';

wait for 30 ns;

A <= "00000000", "00000001" after 2 ns;

wait for 10 ns;

WE_L <= '1';


wait for 3 ns;

A    <= (others => 'X');
D    <= (others => 'Z');

wait for 10 ns;
                                    
                                    

-----------------------------

print(" ");
print(" unstable data");

A    <= "00000000";
D    <= "11110000";

wait for 4 ns;

WE_L <= '0';

wait for 30 ns;

D    <= "00000000";

wait for 10 ns;

WE_L <= '1';


wait for 3 ns;

A    <= (others => 'X');
D    <= (others => 'Z');

wait for 10 ns;
                                    
 

-----------------------------

print(" ");
print(" one correct access");

A    <= "00000001";
D    <= "00001111";

wait for 4 ns;

WE_L <= '0';

wait for 40 ns;

WE_L <= '1';

wait for 3 ns;

A    <= (others => 'X');
D    <= (others => 'Z');

wait for 10 ns;
                                    

wait;


     
end process test_seq;


 
end test;