library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_arith.all;

use work.txt_util.all;
 
 
entity SIMPLE_SRAM is
   port(
        A:      in  std_logic_vector(7 downto 0);
        WE_L:   in  std_logic;
        
        D:      inout  std_logic_vector(7 downto 0)
       );
end SIMPLE_SRAM; 


-- I/O Dictionary
--
-- A:          Address bus
-- WE_L:       Write Enable
-- D:          Data bus
--
--


architecture transactor of SIMPLE_SRAM is


constant tSU       : time :=  4 ns;
constant tH        : time :=  3 ns;
constant tW_WE     : time := 40 ns;


signal add_hold: boolean := false;
signal dat_hold: boolean := false;
signal add_val:  std_logic_vector(A'range);
signal dat_val:  std_logic_vector(D'range);
 
begin

-- hold time monitors
add_monitor: process
begin
  
  wait until A'event;
  
  assert not add_hold or A = add_val
    report "E@SIMPLE_SRAM: Address hold time violated"
    severity Error;
   
end process add_monitor;


dat_monitor: process
begin
  
  wait until D'event;
  
  assert not dat_hold or D = dat_val
    report "E@SIMPLE_SRAM: Data hold time violated"
    severity Error;
   
end process dat_monitor;





test_prg: process


procedure write(wadd: std_logic_vector(7 downto 0);
                wdat: std_logic_vector(7 downto 0)
              ) is 

  variable start_cycle: time;

 begin

   D <= (others => 'Z');
   
   wait until WE_L = '0';
   
   start_cycle := now;
   
   -- check setup times
   assert A'last_event >= tSU
     report "E@SIMPLE_SRAM: Address setup time violated"
     severity Error;
   
   assert D'last_event >= tSU
     report "E@SIMPLE_SRAM: Data setup time violated"
     severity Error;
     
   -- report action for transaction log                
   print("I@SIMPLE_SRAM: "& hstr(D)& "h written to "& hstr(A)& "h");
   
   -- verify address
   assert A = wadd
     report "E@SIMPLE_SRAM: Address incorrect, expected "& 
             str(wadd)& " received "& str(A)
     severity Error;
   
   
   -- verify data
   for i in wdat'range loop
      if wdat(i) /= '-' and wdat(i) /= D(i) then
         print("E@SIMPLE_SRAM: Write Data Invalid, written data = "& str(D)&
               " expected data = "& str(wdat) );
         exit;
      end if;  
   end loop;

              
   wait until WE_L = '1';
   
   
   -- verify pulse width on WE_L
   assert now - start_cycle >= tW_WE
     report "E@SIMPLE_SRAM: WE_L pulse width violated"
     severity Error;
   
   -- verify address and data haven't changed during the cycle
   assert A'last_event >= (now - start_cycle)
     report "E@SIMPLE_SRAM: Address hold time violated"
     severity Error;
   
   assert D'last_event >= (now - start_cycle)
     report "E@SIMPLE_SRAM: Data hold time violated"
     severity Error;
     
   
   -- now make sure the hold times are maintained  
   add_hold <= true, false after tH;
   dat_hold <= true, false after tH;
   add_val  <= A;
   dat_val  <= D;
       
 end write; 



procedure read(radd: std_logic_vector(A'range);
               rdat: std_logic_vector(D'range)) is 
 begin

          
end read; 


begin

-- Test Program
----------------

write("00000000", "11110000");
write("00000001", "00001111");


------------
-- End Test



end process test_prg;

 
end transactor;