-- -------------------------------------------------------------------
--
--   Simple microprocessor model 
--
-- -------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.conv_integer;

use std.textio.all;
use work.txt_util.all;
 
 
entity MP is
   port(
        RST:    in   std_logic;
        A:      out  std_logic_vector(7 downto 0);
        WE_L:   out  std_logic;
        RD_L:   out  std_logic;
        D:      inout  std_logic_vector(7 downto 0)
       );
end MP; 


architecture test of MP is


constant tSU       : time :=  4 ns;
constant tH        : time :=  3 ns;
constant tW_WE     : time := 40 ns;
constant tRD       : time :=  6 ns;
constant tW_RD     : time := 40 ns;

begin



transactor: process

procedure write(wadd: std_logic_vector(A'range); 
                wdat: std_logic_vector(D'range);
                flag: string) is
begin
   
   print("I@MP: write "& hstr(wdat)& "h to "& hstr(wadd)& "h");

   A    <= wadd;
   D    <= wdat;

   wait for tSU;

   WE_L <= '0';
   if flag = "weak" then
      WE_L <= 'L';
   end if;
   
   wait for tW_WE;

   WE_L <= '1';
   if flag = "weak" then
      WE_L <= 'H';
   end if;

   wait for tH;

   A    <= (others => 'X');
   D    <= (others => 'Z');
   
end procedure write;



procedure write(wadd: std_logic_vector(A'range); 
                wdat: std_logic_vector(D'range)) is
begin
   write(wadd, wdat, "none");
end procedure write;




procedure read(radd: std_logic_vector(A'range); 
               rdat: std_logic_vector(D'range);
               flag: string) is
begin
   

   A    <= radd;
   D    <= (others => 'Z');

   wait for tSU;

   RD_L <= '0';
   if flag = "weak" then
      RD_L <= 'L';
   end if;
   
   wait for tW_RD;
                           
   RD_L <= '1';
   if flag = "weak" then
      RD_L <= 'H';
   end if;
   print("I@MP: read "& hstr(D)& "h from "& hstr(radd)& "h");
   assert D = rdat
     report "E@MP: read incorrect value"
     severity Error;

   wait for tH;

   A    <= (others => 'X');
   
end procedure read;



procedure read(radd: std_logic_vector(A'range); 
               rdat: std_logic_vector(D'range)) is
begin
   read(radd, rdat, "none");
end procedure read;



begin


A    <= (others => 'X');
D    <= (others => 'Z');
WE_L <= '1';
RD_L <= '1';
  
  
wait until RST='1';
wait until RST='0';

write("00001111","10101111");
wait for 5 ns;
read("00001111","10101111");
wait for 5 ns;

-- fill up model space
for i in 0 to 32 loop
   write(conv_std_logic_vector(i,8),conv_std_logic_vector(i,8));
end loop;

-- read back all locations
for i in 0 to 33 loop
   read(conv_std_logic_vector(i,8),conv_std_logic_vector(i,8));
end loop;

print(" ");
print("change the values of existing addresses");
print(" ");

write("00000011","10101111");
write("00000010","00000000");

print(" ");
print("and verify the changes");
print(" ");
read("00000011","10101111");
read("00000010","00000000");

print(" ");
print("do two weak writes");
print(" ");
write("00000100","10101010","weak");
write("00000101","01010101","weak");

print(" ");
print("do two weak reads");
print(" ");
read("00000100","10101010","weak");
read("00000101","01010101","weak");


wait;


end process transactor;


 
end test;