-- -------------------------------------- -- Reads std_logic values from a file -- and interprets simple commands -- -------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use std.textio.all; use work.txt_util.all; entity FILE_READ2 is generic ( stim_file: string := "sim.cmd" ); port( CLK : in std_logic; RST : in std_logic; Y : out std_logic_vector(4 downto 0); EOG : out std_logic ); end FILE_READ2; -- I/O Dictionary -- -- Inputs: -- -- CLK: new cell needed -- RST: reset signal, wait with reading till reset seq complete -- -- Outputs: -- -- Y: Output vector -- EOG: End Of Generation, all lines have been read from the file -- architecture read_from_file of FILE_READ2 is file stimulus: TEXT open read_mode is stim_file; begin -- read data and control information from a file receive_data: process variable l: line; variable s: string(1 to 80); variable c: character; variable in_string: boolean; begin EOG <= '0'; wait until RST='1'; wait until RST='0'; while not endfile(stimulus) loop --*-- read variable length string --*-- from input file --*readline(stimulus, l); --*s := (others => ' '); --*for i in s'range loop --* read(l, c, in_string); --* s(i) := c; --* if not in_string then -- found end of line --* exit; --* end if; --*end loop; str_read(stimulus, s); if s(1 to 6) = "#count" then -- check for command "count" for i in 1 to 5 loop Y <= conv_std_logic_vector(i,5); wait until CLK = '1'; end loop; else -- if it's not a command -> process data normally Y <= to_std_logic_vector(s(1 to 5)); wait until CLK = '1'; end if; end loop; print("I@FILE_READ: reached end of "& stim_file); EOG <= '1'; wait; end process receive_data; end read_from_file;