System01 - VHDL 6801
22nd October 2002 12:11am
System01 is a MC6801 clone. it prints out my standard
"Hello World" message but as of 12:11 am on 22 Oct 2002 it has
not been tested beyond that. next step is to try and write a monitor
program for it and try loading Flex 2. Note: I have not
implemented the 8 bit multiply on it as yet. The mini UART sits at $E010.
A parallel I/O port sits at $E000 and works as per the 6805. ie 4 x 8
bit data ports and 4 x 8 bit data direction registers. A mock up timer
has been added at $E008 but it does not do anything.
23rd October 2002 11:45 am
I've included the SWTBUG monitor program at $E000 and I
re-origined the I/O devices to $8000 in accordance with the original
6800 SWTPC. The SWTBUG listing I got off Michael Holley's SWTPC
web site http://www.swtpc.com
The ACIA now sites at $8004, timer at $8000 (It does not do anything) and
4 x 8 bit port at $8008 / $800C. There was also a bug in the opcode decoding
on ACCB. All it does at the moment is spit out ASCII '4' which I think is
part of the PIA initialisation ... It seems to be polling the Mini UART which
should look a little like a 6850 ACIA, but might be mistaking it for a PIA.
28th October 2002 4:53 pm
First off, the ROM I used in SwtSys01.zip includes MIKBUG,
which explains why it was polling the uart at $8004 incorrectly.
It should only be 1 Kbyte long, not 2Kbytes. I've also done a major
rework of the condition codes. The 6801 CPX instruction sets the Carry
Flag where as the 6800 does not. This can upset things like the SWTP
4K Basic apparently. I'm going to release a System68 version shortly
that is true to the 6800 condtion codes (hopefully). On the 6801, I
used the same 16 bit subtract for SUBD in the ALU as the CPX.
The baudrate of the miniuart is set to 19.2Kbps which
is too fast to download S1 records. You will have to insert a character
delay of 1 msec in hyperterm to get S1 records to load, but this
will slow Hyperterm down incredibly and make it run at 300Bd.
14th January 2004
Michael Hasenfratz is working on System6801 on the opencores
web site. He has ported the code to an Altera board. He has located a
bug in the CPU01 core where the CLR does not clear the carry. This is
because the state sequencer enumerates a "alu_ld8" instead of an
"alu_clr" on the ALU control line. "alu_ld8" will clear the register or
memory, but will not affect the carry. I think I have fixed that
problem in this release.
I've now ported system01 to the BurchED B5-X300 board and am using
Xilinx Web Pack ISE 6.1 (I think). I've change the Clock edge to a
negative edge. This was an error I found some time back on the System68
and I thought I'd fixed it up in System01 but it did not look like I
had.
I've added a compact flash interface to be consistant with the other
designs. I've also removed the test_alu and test_cc signals so I could
use connectors H and G for the four 8 bit parallel I/O ports. The
Compact Flash registers are mapped at $8010 - $801F. Note that I have
allocated 16 bytes per I/O device as the SWTPC 6809's do. The UART sits
at $8000 - $800F, but by convention it is addressed at $8004/$8005.
I've mapped timers and parallel I/O at the bottom of memory, but it is
also dual mapped up at $8020-$802F. It is not possible to run FLEX2
programs on a 6801 because of the I/O in the base page, so at some
stage I might put
a switch in the I/O map at $8030 to relocate or disable the base page I/O.
ICST525-01 PLL Clock divider:
Check out the web site http://www.icst.com/products/ics525inputForm.html
for a frequency calculator for ICST525-01 PLL chip. Given
a 20 MHz Xtal oscillator, the ICST525-01 PLL should use the following
dividers to generate a 4.915254 MHz clock:
0 = link in (grounded)
1 = link out (pulled high)
V8
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V7
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V6
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V5
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V4
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V3
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V2
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V1
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V0
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NU
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0
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0
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0
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1
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1
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0
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0
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1
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0
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R0
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R1
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R2
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R3
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R4
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R5
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R6
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S0
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S1
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S2
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1
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0
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0
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1
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1
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1
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0
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0
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1
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0
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